Non Blocking Assignment

Part of the Fundamentals section of Coddy's Verilog journey — lesson 50 of 90.

In the previous lesson, we covered blocking assignment (=), which executes step by step. Now we will cover non-blocking assignment (<=), which executes all at once — in parallel.

Non-blocking assignment uses the <= operator. It is called "non-blocking" because it does not block the execution of the next statement. All non-blocking assignments in a block execute at the same time.

Syntax:

variable <= expression;

When to Use Non-Blocking Assignment

Non-blocking assignment (<=) is used for sequential logic — circuits that use a clock and have memory. Outputs change only on a clock edge (usually the rising edge).

Examples of sequential logic:

Flip-flops
Registers
Counters

State machines
Shift registers

Verilog example:

initial begin
  a <= 5;      // Scheduled, but not executed yet
  b <= a + 2;  // Scheduled, uses OLD value of a
  c <= b * 3;  // Scheduled, uses OLD value of b
end

All three assignments happen at the same time using the old values. At the end of the time step, all updates happen together.

Non-Blocking in Always Blocks (Sequential Logic)

Non-blocking is used for sequential logic — circuits that use a clock and have memory (flip-flops, registers, counters).

always @(posedge clk) begin
  q <= d;           // q gets d on clock edge
  count <= count + 1; // count increments on clock edge
end

Both assignments happen at the same time, using values from before the clock edge.

Summary

Rule	Explanation
Use `<=` for sequential logic	`always @(posedge clk)`
Use `=` for combinational logic	`always @(*)`
Non-blocking executes in parallel	All assignments happen at once
Values update at end of time step	Not immediately

Challenge

Complete the Non-Blocking Assignment

Add the missing non-blocking assignments to make this 2-bit shift register work.

How it works:

On each clock edge, q1 gets d
q2 gets the old value of q1

What to do:

Assign d to q1 (non-blocking)
Assign q1 to q2 (non-blocking)

Cheat sheet

Non-blocking assignment (<=) executes all statements in parallel — using old values, updating at the end of the time step.

// All use OLD values of a and b
a <= 5;
b <= a + 2;  // uses old a
c <= b * 3;  // uses old b

Use <= for sequential logic (flip-flops, registers, counters) inside clocked always blocks:

always @(posedge clk) begin
  q     <= d;           // non-blocking
  count <= count + 1;   // non-blocking
end

Assignment	Use for	Executes
`<=`	Sequential logic (`posedge clk`)	In parallel
`=`	Combinational logic (`always @(*)`)	Step by step

Try it yourself

module shift_register (
  input clk,
  input reset,
  input d,
  output reg q1,
  output reg q2
);
  
  always @(posedge clk or posedge reset) begin
    if (reset) begin
      q1 <= 0;
      q2 <= 0;
    end else begin
      // TODO: Add shift logic
      // Step 1: Assign d to q1 (non-blocking)
      // Step 2: Assign q1 to q2 (non-blocking)
    end
  end
endmodule