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Blocking Assignment

Part of the Fundamentals section of Coddy's Verilog journey — lesson 49 of 90.

Verilog has two types of procedural assignments: blocking (=) and non-blocking (<=). In this lesson, we focus on blocking assignment.

Blocking assignment uses the = operator. It is called "blocking" because it blocks the execution of the next statement until the current assignment is complete. The code runs step by step, in order.

Syntax:

variable = expression;

When to Use Blocking Assignment

Blocking assignment (=) is used for combinational logic — circuits where outputs change immediately when inputs change, with no clock and no memory.

Examples of combinational logic:

  • AND / OR / XOR gates
  • Adders and subtractors
  • Multiplexers
  • Decoders

Verilog example:

always @(*) begin
  sum = a + b;      // Blocking assignment
  carry = a & b;    // Blocking assignment
end

Blocking in Always Blocks (Combinational Logic)

always @(*) begin
  temp = a & b;    // Step 1
  out = temp | c;  // Step 2 (uses temp from step 1)
end

The order matters. This is fine for combinational logic.

Blocking vs Non-Blocking

 Blocking (=)Non-blocking (<=)
ExecutionOne after anotherAll at once
Next line waits?YesNo
UsesCombinational logicSequential logic (flip-flops)

Important: Do Not Use Blocking for Flip-Flops

challenge icon

Challenge

Add the missing blocking assignments to swap the values of x and y using a temporary variable.

What to do:

  1. Assign the value of x to temp (save x in temp)
  2. Assign the value of y to x (move y into x)
  3. Assign the value of temp to y (move saved x into y)

Cheat sheet

Blocking assignment (=) executes sequentially — each statement completes before the next begins. Used for combinational logic inside always @(*) blocks.

always @(*) begin
  temp = a & b;    // Step 1
  out = temp | c;  // Step 2 (uses updated temp)
end
Blocking (=) Non-blocking (<=)
Execution One after another All at once
Use for Combinational logic Sequential logic (flip-flops)

Try it yourself

module swap;
  reg x, y;
  reg temp;
  
  initial begin
    x = 1;
    y = 0;
    
    $display("Before swap: x=%d, y=%d", x, y);
    
    // TODO: Step 1 - Assign x to temp
    
    // TODO: Step 2 - Assign y to x
    
    // TODO: Step 3 - Assign temp to y
    
    $display("After swap: x=%d, y=%d", x, y);
    $finish;
  end
endmodule
quiz iconTest yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

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