AND OR NOT Gates

Part of the Fundamentals section of Coddy's Verilog journey — lesson 40 of 90.

This lesson covers the three most basic logic gates: AND, OR, and NOT. These gates form the foundation of digital logic design.

AND Gate

The AND gate outputs 1 only when all inputs are 1.

Truth Table (2-input):

a	b	out
0	0	0
0	1	0
1	0	0
1	1	1

Verilog gate primitive:

and(out, a, b);

Continuous assignment equivalent:

assign out = a & b;

OR Gate

The OR gate outputs 1 when at least one input is 1.

Truth Table (2-input):

a	b	out
0	0	0
0	1	1
1	0	1
1	1	1

Verilog gate primitive:

or(out, a, b);

Continuous assignment equivalent:

assign out = a | b;

NOT Gate

The NOT gate outputs the opposite of its single input. It is also called an inverter.

Truth Table:

a	out
0	1
1	0

Verilog gate primitive:

not(out, a);

Continuous assignment equivalent:

assign out = ~a;

Multiple Inputs

AND and OR gates can have more than 2 inputs:

and(out, a, b, c);     // 3-input AND (out = a & b & c)
or(out, x, y, z, w);   // 4-input OR

NOT gates always have exactly 1 input.

Code Example

module and_or_not (
  input a, b,
  output and_out,
  output or_out,
  output not_out
);
  and(and_out, a, b);   // AND gate
  or(or_out, a, b);     // OR gate
  not(not_out, a);      // NOT gate (inverter)
endmodule

Challenge

Add the missing gate primitives based on the tasks.

What to do:

Create an AND gate with output and_result and inputs p and q
Create an OR gate with output or_result and inputs p and q
Create a NOT gate with output not_result and input p

Cheat sheet

Basic logic gates in Verilog using gate primitives and continuous assignment:

Gate	Primitive	Assign	Output is 1 when...
AND	`and(out, a, b);`	`assign out = a & b;`	All inputs are 1
OR	`or(out, a, b);`	`assign out = a \| b;`	At least one input is 1
NOT	`not(out, a);`	`assign out = ~a;`	Input is 0

AND and OR support more than 2 inputs; NOT always has exactly 1 input:

and(out, a, b, c);   // 3-input AND
or(out, a, b, c, d); // 4-input OR

module example (input a, b, output and_out, or_out, not_out);
  and(and_out, a, b);
  or(or_out, a, b);
  not(not_out, a);
endmodule

Try it yourself

module gates_challenge (
  input p,
  input q,
  output and_result,
  output or_result,
  output not_result
);
  
  // TODO: Add AND gate (and_result = p & q)
  
  // TODO: Add OR gate (or_result = p | q)
  
  // TODO: Add NOT gate (not_result = ~p)

endmodule