Your First Module

Part of the Fundamentals section of Coddy's Verilog journey — lesson 4 of 90.

A module is the basic building block in Verilog. Every piece of Verilog code is inside a module.

Think of a module as a component with:

Inputs (signals coming in)
Outputs (signals going out)
Behavior (what it does)

Module Syntax

module module_name ( inputs, outputs );

  // Everything inside here

endmodule

Every module starts with module and ends with endmodule.

Inputs and Outputs

module and_gate(
  input a,     // a comes INTO the module
  input b,     // b comes INTO the module
  output c     // c goes OUT of the module
);

  // Behavior goes here

endmodule

input = signal enters the module
output = signal leaves the module

Adding Behavior

Now we make the module do something:

module and_gate(
  input a,
  input b,
  output c
);

  assign c = a & b;  // c is 1 only when a AND b are 1

endmodule

assign continuously connects the right side to the left side
& means AND in Verilog

Challenge

In this challenge, you need to create a simple module that performs the OR operation.

What to do:

The module should be named or_gate
It should have an input called x
It should have an input called y
It should have an output called z
Inside the module, use assign to make z equal to x OR y

The module header and its three ports are already in the editor. The line you need to add is the assign statement inside the module.

Note: In Verilog, OR is written with the pipe symbol |. It outputs 1 (true) if at least one of the inputs is 1 (true).

Try it yourself

// The module header and its ports are already written for you
module or_gate(
  input x,
  input y,
  output z
);

  // Your turn: use assign to set z to x OR y
  // In Verilog, OR is written as |

endmodule