Your First Module

Part of the Fundamentals section of Coddy's Verilog journey — lesson 4 of 90.

A module is the basic building block in Verilog. Every piece of Verilog code is inside a module.

Think of a module as a component with:

Inputs (signals coming in)
Outputs (signals going out)
Behavior (what it does)

Module Syntax

module module_name ( inputs, outputs );

  // Everything inside here

endmodule

Every module starts with module and ends with endmodule.

Inputs and Outputs

module and_gate(
  input a,     // a comes INTO the module
  input b,     // b comes INTO the module
  output c     // c goes OUT of the module
);

  // Behavior goes here

endmodule

input = signal enters the module
output = signal leaves the module

Adding Behavior

Now we make the module do something:

module and_gate(
  input a,
  input b,
  output c
);

  assign c = a & b;  // c is 1 only when a AND b are 1

endmodule

assign continuously connects the right side to the left side
& means AND in Verilog

Challenge

In this challenge, you need to create a simple module that performs the OR operation.

What to do:

The module should be named or_gate
It should have an input called x
It should have an input called y
It should have an output called z
Inside the module, use assign to make z equal to x OR y

Note: In Verilog, OR is written with the pipe symbol |. It outputs 1 (true) if at least one of the inputs is 1 (true).

Cheat sheet

A module is the basic building block in Verilog, acting as a component with inputs, outputs, and behavior.

module module_name (
  input a,
  input b,
  output c
);

  // behavior

endmodule

Use assign to continuously drive an output signal:

assign c = a & b;  // AND
assign c = a | b;  // OR

& — AND operator
| — OR operator

Try it yourself

// Step 1: Create a module named or_gate

  // Step 2: Create input x

  // Step 3: Create input y

  // Step 4: Create output z

  // Step 5: Use assign to make z = x OR y
  // In Verilog, OR is written as |