Writing The Testbench

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 45 of 90.

Challenge

Now we need to test if the half adder is working correctly. Add the test code inside the initial block.

Important: Before adding the test, you must change the module ports so the test can work properly.

What to do:

Step 1: Change the port declarations

Change input a, b to reg a, b (use the semicolon)
Change output sum, carry to wire sum, carry (use the semicolon)
Remove the module ports entirely (the module should have no ( ))

Step 2: Add the test code

Add an initial begin block
Inside the block, add:

$display("a b | sum carry"); 
a = 0; b = 0; #1 $display("%d %d |  %d    %d", a, b, sum, carry); 
a = 0; b = 1; #1 $display("%d %d |  %d    %d", a, b, sum, carry); 
a = 1; b = 0; #1 $display("%d %d |  %d    %d", a, b, sum, carry); 
a = 1; b = 1; #1 $display("%d %d |  %d    %d", a, b, sum, carry);

Add $finish; to end the test
Add end to close the initial block

Try it yourself

module half_adder (
  input a,
  input b,
  
  output sum,
  output carry
);
  assign sum = a ^ b;
  assign carry = a & b;
  
endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Your First Module Comments Design Abstraction Levels

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays Parameters Recap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The Module Designing The Logic

Writing The Testbench Project lesson

11Loops

For Loop While Loop Repeat Loop Forever Loop Disable Statement Recap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counter State Machine

Transmitter Design

Testbench

Practice on your own: Online Verilog compiler