What Are Delays

Part of the Fundamentals section of Coddy's Verilog journey — lesson 67 of 90.

In Verilog, delays control when a statement executes or when a signal changes. They are used to model real hardware timing behavior.

Why Delays Are Needed

Real hardware takes time for signals to travel through wires and gates. Delays allow you to simulate this timing behavior.

In simulation, without delays, everything happens at time 0
Delays let you space out events over time
They help test timing-sensitive designs like clocks and state machines

Types of Delays

Delay Type	Purpose
Gate Delays	Delay through logic gates
Assignment Delays	Delay when assigning values
Timescale Directive	Sets time units for simulation

Basic Syntax

A delay is written with a # followed by a number:

#10 clk = ~clk;   // Wait 10 time units, then toggle clock
#5 a = b;         // Wait 5 time units, then assign a = b

The number after # is the number of time units to wait.

Simple Example

initial begin
  a = 0;
  #10 a = 1;   // After 10 time units, a becomes 1
  #5 a = 0;    // After another 5 time units, a becomes 0
end

Timing:

Time 0: a = 0
Time 10: a = 1
Time 15: a = 0

Delays in Always Blocks

always #5 clk = ~clk;   // Toggle clock every 5 time units

This creates a continuous clock signal.

Important Rules

Rule	Explanation
`#` symbol	Marks a delay
Number after `#`	How many time units to wait
Delays are cumulative	`#10` then `#20` waits total 30
Not synthesizable	Delays are for simulation only

Challenge

What to do:

Add the missing delays to make this code print messages at times 0, 10, 25, and 40.

Cheat sheet

In Verilog, delays use # followed by time units to control when statements execute:

#10 a = 1;   // Wait 10 time units, then assign

Delays are cumulative — each delay adds to the current time:

initial begin
  a = 0;      // Time 0
  #10 a = 1;  // Time 10
  #5  a = 0;  // Time 15
end

Use in always blocks to generate clocks:

always #5 clk = ~clk;  // Toggle every 5 units

Note: Delays are for simulation only — not synthesizable.

Try it yourself

module delay_challenge;
  
  initial begin
    $display("Time %0t: Start", $time);
    // TODO: Add delay to reach time 10
    $display("Time %0t: After first delay", $time);
    // TODO: Add delay to reach time 25
    $display("Time %0t: After second delay", $time);
    // TODO: Add delay to reach time 40
    $display("Time %0t: End", $time);
    $finish;
  end
  
endmodule