Recap - Declare Signals

Part of the Fundamentals section of Coddy's Verilog journey — lesson 12 of 90.

Challenge

Add the missing signal declarations based on what you learned in this chapter.

What to do:

Declare an 8-bit wire called data
Declare a 4-bit reg called counter
Declare an integer called i
Declare a parameter called MAX with value 255

Try it yourself

module data_types;
  // Declare an 8-bit wire called data
  
  // Declare a 4-bit reg called counter
  
  // Declare an integer called i
  
  // Declare a parameter called MAX with value 255
  
endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays ParametersRecap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The Module Designing The Logic

Writing The Testbench

11Loops

For Loop While Loop Repeat Loop Forever Loop Disable Statement Recap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counter State Machine

Transmitter Design

Testbench