Recap - Timing Control

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 72 of 90.

Challenge

This challenge tests your understanding of delays, gate delays, assignment delays, timescale, and clock generation.

What to do:

Add a timescale directive with 1ns / 1ps
Generate a clock that toggles every 5 time units
Add an AND gate with a 3 time unit gate delay
Use an assignment delay to assign a to b after 2 time units (read a immediately)

Try it yourself

// TODO: Add timescale directive (1ns / 1ps)


module timing_challenge;
  reg clk;
  reg a, b;
  wire out;
  
  initial begin
    clk = 0;
  end
  
  // TODO: Generate clock that toggles every 5 time units
  
  
  // TODO: Add AND gate with 3 time unit delay (inputs a, b, output out)
  
  
  initial begin
    $monitor("Time %0t: clk=%b, a=%b, b=%b, out=%b", $time, clk, a, b, out);
    
    a = 1;
    
    // TODO: Use assignment delay to assign a to b after 2 time units
    // Read a now, assign to b after 2 time units
    
    
    #20;
    $finish;
  end
endmodule