Special Values X And Z

Part of the Fundamentals section of Coddy's Verilog journey — lesson 17 of 90.

X and Z are special values that give us information about the hardware state during simulation.

X (Unknown) — For Debugging

X appears in simulation to indicate problems with your design.

When you see X, it often means:

Uninitialized register — you forgot to set a value before using it
Multiple drivers — two different things are trying to control the same wire at the same time
Timing violation — a signal changed at the wrong time, creating an unstable state

X does not exist in real hardware. It is a simulation tool that tells you something is wrong with your design so you can fix it before building the actual chip.

Without X, you might see random 0s or 1s and not realize there's a problem. X makes bugs visible.

Common causes:

reg a;           // Initially X (unknown)
reg b;
assign b = a;    // b becomes X because a is X

Z (High Impedance)

Z represents a high-impedance or disconnected state.

A signal is Z when it is not being driven by anything
Z means "this wire is disconnected"
Used for tri-state buffers and shared buses

Common causes:

wire c;          // Initially Z (not connected)
assign c = 1'bZ; // Explicitly set to Z

Writing X and Z in Verilog

You can assign X and Z values just like 0 and 1:

reg [3:0] data;

data = 4'b10X0;    // Bit 1 is unknown (0-indexed from the right)
data = 4'b01Z1;    // Bit 1 is high-impedance
data = 4'bXXXX;    // All bits unknown
data = 4'bZZZZ;    // All bits high-impedance

X and Z in Waveforms

In simulation waveforms:

X appears as a red line or "X"
Z appears as a line in the middle or "Z"

These help you debug your design by showing where signals are unknown or disconnected.

Important Notes

X spreads through logic (X AND 0 = 0, but X AND 1 = X)
Z is usually used for tri-state buses
In synthesis, X and Z may be treated differently

Always initialize reg signals to avoid X in simulation

Challenge

Complete the code by writing the correct values containing X and Z.

What to do:

Set a to a 4-bit value where bit 1 is unknown (others 0)
Set c to all bits unknown (4 bits)
Set d to all bits high-impedance (4 bits)

Cheat sheet

X (Unknown) and Z (High-Impedance) are special simulation values in Verilog.

X — Unknown state (simulation only, not real hardware):

Uninitialized reg starts as X
Caused by: uninitialized registers, multiple drivers, timing violations
Spreads through logic (X AND 1 = X, but X AND 0 = 0)
Appears as red line in waveforms

Z — High-impedance / disconnected state:

Undriven wire starts as Z
Used for tri-state buffers and shared buses
Appears as middle line in waveforms

Writing X and Z in Verilog:

reg [3:0] data;

data = 4'b10X0;    // Bit 1 is unknown
data = 4'b01Z1;    // Bit 1 is high-impedance
data = 4'bXXXX;    // All bits unknown
data = 4'bZZZZ;    // All bits high-impedance

assign c = 1'bZ;   // Explicitly set wire to Z

Try it yourself

module xz_challenge;
  wire [3:0] a, c, d;
  
  assign a = 4'b______;   // Bit 1 is X (others 0)
  assign c = 4'b______;   // All bits X
  assign d = 4'b______;   // All bits Z
  
  initial begin
    $display("a = %b", a);
    $display("c = %b", c);
    $display("d = %b", d);
    $finish;
  end
  
endmodule