Transmitter Design

Part of the Fundamentals section of Coddy's Verilog journey — lesson 89 of 90.

Challenge

In this lesson, you will complete the UART transmitter by adding the shift register to send any byte, not just the fixed letter 'A'.

The shift register loads the full frame (stop bit + 8 data bits + start bit) and shifts it out one bit at a time.

Frame Format

Stop (1)	Data (8 bits)	Start (0)
1	`data_in`	0

For example, if data_in = 8'b01000001 (letter 'A'), the shift register becomes: 1 01000001 0

Your Task

You are given the state machine from the previous lesson (transmits fixed byte). You need to modify it to send any byte from the data_in input.

What to do:

Add an input [7:0] called data_in to the port list (inside the parentheses)
Add a 10-bit reg called shift_reg outside the parentheses (inside the module body, because it is an internal signal)
When cnt == 0 and start == 1:
1. Load shift_reg with {1'b1, data_in, 1'b0}
When cnt is between 1 and 8:
1. Send tx <= shift_reg[0]
2. Shift right: shift_reg <= shift_reg >> 1
When cnt == 9:
1. Send tx <= shift_reg[0]
2. Shift right: shift_reg <= shift_reg >> 1

Try it yourself

module uart_tx (
  input clk,
  input start,           // NEW: start signal to begin transmission
  output reg tx,         // NEW: serial output line
  output reg [3:0] cnt   // Keep as output for testing
);

  initial begin
    cnt = 0;
    tx = 1;              // NEW: set tx HIGH (idle state)
  end

  always @(posedge clk) begin
    // NEW: Counter logic with start condition
    if (cnt == 0 && start) begin   // NEW: start transmitting
      cnt <= 1;
    end
    else if (cnt > 0 && cnt < 9) begin   // NEW: count while transmitting
      cnt <= cnt + 1;
    end
    else if (cnt == 9) begin      // NEW: reset after last bit
      cnt <= 0;
    end
  end

endmodule