4 To 1 Mux Design

Part of the Fundamentals section of Coddy's Verilog journey — lesson 65 of 90.

Challenge

4-to-1 Multiplexer

The 4-to-1 multiplexer has four data inputs (in0, in1, in2, in3), two select bits (sel[1:0]), and one output (out). The two select bits choose which input passes to the output:

When sel = 2'b00, output is in0
When sel = 2'b01, output is in1
When sel = 2'b10, output is in2
When sel = 2'b11, output is in3

You will build this multiplexer in two ways: first using if-else statements, then in the next lesson using a case statement. Both methods work, but case is often cleaner when you have many choices.

A 4-to-1 multiplexer selects one of four inputs and passes it to the output based on a 2-bit select signal.

Truth Table

sel1	sel0	out
0	0	out = in0
0	1	out = in1
1	0	out = in2
1	1	out = in3

When sel is 00, output follows in0. When sel is 01, output follows in1. When sel is 10, output follows in2. When sel is 11, output follows in3.

What to do:

Create a module named mux4to1
Add input in0 (1 bit)
Add input in1 (1 bit)
Add input in2 (1 bit)
Add input in3 (1 bit)
Add input sel (2 bits)
Add output out (1 bit, type reg)
Add an always @(*) block
Inside, add an if-else statement checking sel:
- If sel == 2'b00, set out = in0
- Else if sel == 2'b01, set out = in1
- Else if sel == 2'b10, set out = in2
- Else, set out = in3
Close with endmodule

Try it yourself

// Step 1: Create module named mux4to1


  // Step 2: Add input in0
  
  // Step 3: Add input in1
  
  // Step 4: Add input in2
  
  // Step 5: Add input in3
  
  // Step 6: Add input sel (2 bits)
  
  // Step 7: Add output out (reg type)
  

  // Step 8: Add always @(*) block
  

    // Step 9: Add if-else statement
    // if sel == 2'b00, out = in0
    // else if sel == 2'b01, out = in1
    // else if sel == 2'b10, out = in2
    // else, out = in3
    

// Step 10: Endmodule