Shift Operators

Part of the Fundamentals section of Coddy's Verilog journey — lesson 26 of 90.

Shift operators move bits left or right within a vector.

Available Shift Operators

Operator	Operation	Description
`<<`	Logical left shift	Shifts bits left, fills with zeros
`>>`	Logical right shift	Shifts bits right, fills with zeros
`<<<`	Arithmetic left shift	Same as logical left shift
`>>>`	Arithmetic right shift	Shifts right, preserves sign bit

How They Work

Left Shift (<strong><<</strong>):

8'b00001010 << 2 = 8'b00101000

Bits move left. Zeros fill the right side.

Right Shift (<strong>>></strong>):

8'b00001010 >> 2 = 8'b00000010

Bits move right. Zeros fill the left side.

Code Example

module shift_demo;
  reg [7:0] original, left_shift, right_shift;
  
  initial begin
    original = 8'b00001010;
    
    left_shift  = original << 2;   // 00001010 → 00101000
    right_shift = original >> 2;   // 00001010 → 00000010
    
    $display("original   = %b", original);
    $display("<< 2       = %b", left_shift);
    $display(">> 2       = %b", right_shift);
    $finish;
  end
endmodule

Output:

original   = 00001010
<< 2       = 00101000
>> 2       = 00000010

Arithmetic Right Shift (`>>>`)

For signed numbers, arithmetic right shift preserves the sign bit:

reg signed [7:0] a;
a = -5;                // 11111011
a >>> 2 = 11111110     // Still negative

Logical shift (>>) would fill with zeros and lose the sign.

Common Uses

Multiply by power of 2 (left shift):

x << 1    // Multiply by 2
x << 2    // Multiply by 4
x << 3    // Multiply by 8

Divide by power of 2 (right shift):

x >> 1    // Divide by 2
x >> 2    // Divide by 4
x >> 3    // Divide by 8

Extract a field:

// Get bits 5-2 from an 8-bit value
field = (data >> 2) & 4'b1111;

Challenge

Write the correct shift expressions for each task.

What to do:

Shift a left by 3 bits and store in left_result
Shift a right by 1 bit and store in right_result
Shift b right by 2 bits (arithmetic) and store in arith_result

Cheat sheet

Shift operators move bits left or right within a vector:

Operator	Description
`<<`	Logical left shift (fills with zeros)
`>>`	Logical right shift (fills with zeros)
`<<<`	Arithmetic left shift (same as logical)
`>>>`	Arithmetic right shift (preserves sign bit)

8'b00001010 << 2  // = 8'b00101000
8'b00001010 >> 2  // = 8'b00000010

reg signed [7:0] a;
a = -5;           // 11111011
a >>> 2           // = 11111110 (sign preserved)

Common uses:

x << n    // Multiply by 2^n
x >> n    // Divide by 2^n

// Extract bits 5-2 from an 8-bit value
field = (data >> 2) & 4'b1111;

Try it yourself

module shift_challenge;
  reg [7:0] a;
  reg signed [7:0] b;
  reg [7:0] left_result, right_result;
  reg signed [7:0] arith_result;
  
  initial begin
    a = 8'b00010001;
    b = -8'sd16;       // 11110000 in binary
    
    left_result  = ______;   // Shift a left by 3 bits
    right_result = ______;   // Shift a right by 1 bit
    arith_result = ______;   // Shift b right by 2 bits (arithmetic)
    
    $display("a = %b", a);
    $display("a << 3 = %b", left_result);
    $display("a >> 1 = %b", right_result);
    $display("b = %b", b);
    $display("b >>> 2 = %b", arith_result);
    $finish;
  end
endmodule