Port Mapping By Name

Part of the Fundamentals section of Coddy's Verilog journey — lesson 34 of 90.

In the previous lesson, you learned how to instantiate a module by passing signals in the same order as the ports appear in the module definition. This works, but it has a problem: order matters.

If you accidentally mix up the order, signals connect to the wrong ports. This can be hard to debug.

The Problem with Order Mapping

module or_gate (
  input in1,
  input in2,
  output result
);
  assign result = in1 | in2;
endmodule

// Order mapping - order MUST match
or_gate or1 (input_a, input_b, output_y);  // Correct
or_gate or1 (input_b, input_a, output_y);  // Wrong! Swapped inputs

The second line connects input_b to in1 and input_a to in2 — a subtle bug that is easy to miss.

Solution: Port Mapping By Name

Port mapping by name uses the port name to make connections. The order does not matter because each connection is explicitly labeled.

Syntax:

module_name instance_name (
  .port_name(signal),
  .port_name(signal)
);

The dot . before the port name indicates we are referring to a port inside the module. The signal inside parentheses is what we connect to it.

Example

or_gate or1 (
  .in1(input_a),
  .in2(input_b),
  .result(output_y)
);

This explicitly says:

Port in1 gets signal input_a
Port in2 gets signal input_b
Port result gets signal output_y

Order Does Not Matter

With port mapping by name, you can write the connections in any order:

// All three are IDENTICAL

or_gate or1 (
  .in1(input_a),
  .in2(input_b),
  .result(output_y)
);

or_gate or1 (
  .result(output_y),
  .in1(input_a),
  .in2(input_b)
);

or_gate or1 (
  .in2(input_b),
  .result(output_y),
  .in1(input_a)
);

All do exactly the same thing because each connection is labeled.

Challenge

Complete the instantiation by adding the missing port connections using port mapping by name.

What to do:

Connect port clk to signal clock_signal
Connect port data_in to signal input_data
Connect port data_out to signal output_data

Cheat sheet

Port mapping by name uses .port_name(signal) syntax, making order irrelevant:

module_name instance_name (
  .port_name(signal),
  .port_name(signal)
);

Example:

or_gate or1 (
  .in1(input_a),
  .in2(input_b),
  .result(output_y)
);

The . before the port name refers to a port inside the module; the signal in parentheses is what connects to it. Unlike order mapping, connections can be listed in any order without causing bugs.

Try it yourself

module register (
  input clk,
  input [7:0] data_in,
  output reg [7:0] data_out
);
  always @(posedge clk) begin
    data_out <= data_in;
  end
endmodule

module top (
  input clock_signal,
  input [7:0] input_data,
  output [7:0] output_data
);
  
  register reg1 (
    // TODO: Add port mappings using .port(signal) syntax
  );
  
endmodule