Defining The States

Part of the Fundamentals section of Coddy's Verilog journey — lesson 79 of 90.

Challenge

A traffic light controller is a finite state machine that cycles through different light states (Red, Yellow, Green) with specific timing intervals. A finite state machine (FSM) is a circuit that can be in one of a limited number of states. It changes from one state to another based on inputs or timing.

In this project, you will build a traffic light controller for a simple intersection. The traffic light has three outputs:

Light	Output	Meaning
Red	`red = 1`	Stop
Yellow	`yellow = 1`	Caution
Green	`green = 1`	Go

The lights cycle in this order:

Green → Yellow → Red → Green → …

Timing Sequence

State	Duration	Next State
Green	30 seconds	Yellow
Yellow	10 seconds	Red
Red	40 seconds	Green

In this lesson, you will define the states for the traffic light controller.

A traffic light has three possible states:

State	Light	Code
Green	Green light ON	2'b00
Yellow	Yellow light ON	2'b01
Red	Red light ON	2'b10

Complete the module by adding the missing parts.

What to do:

Define state encoding: 0=Green, 1=Yellow, 2=Red

Declare a 2-bit register called state
Declare a 6-bit register called counter (for timing up to 40 seconds)
Add output assignments:
- When state is 0: green = 1, yellow = 0, red = 0
- When state is 1: green = 0, yellow = 1, red = 0
- When state is 2: green = 0, yellow = 0, red = 1

Try it yourself

module traffic_light (
  input clk,
  input reset,
  output reg red,
  output reg yellow,
  output reg green
);
  // TODO: Task 1 - Declare state register (2 bits)
  
  // TODO: Task 2 - Declare counter register (6 bits)
  

  // TODO: Task 3 - Output assignments using case (state)
  // state 0: green=1, yellow=0, red=0
  // state 1: green=0, yellow=1, red=0
  // state 2: green=0, yellow=0, red=1

endmodule