Built In Gate Primitives

Part of the Fundamentals section of Coddy's Verilog journey — lesson 39 of 90.

Verilog has built-in gate primitives that allow you to describe logic circuits using actual gate symbols. This is called structural modeling — you build circuits by connecting gates, just like drawing a schematic.

Gate primitives are predefined keywords that model basic logic gates. Instead of writing an expression like assign out = a & b, you instantiate a gate:

and(out, a, b);   // AND gate with output out, inputs a and b

General Syntax

gate_type (output, input1, input2, ...);

First argument is always the output
Following arguments are inputs (1 or more, depending on the gate)

Available Gate Primitives

Gate Type	Keyword	Number of Inputs
AND	`and`	2 or more
OR	`or`	2 or more
NOT	`not`	1
NAND	`nand`	2 or more
NOR	`nor`	2 or more
XOR	`xor`	2 or more
XNOR	`xnor`	2 or more

How Gate Primitives Work

When you write and(out, a, b), Verilog creates an AND gate that continuously drives out with the result of a & b. Whenever a or b changes, out updates immediately — just like a real gate.

Gate Primitives vs Continuous Assignment

Both methods produce the same hardware:

// Gate primitive
and(out, a, b);

// Continuous assignment (same result)
assign out = a & b;

Gate primitives are useful when you want to describe a circuit as a collection of gates (structural style). Continuous assignment is better for behavioral style (expressions).

Challenge

What to do:

Add the correct gate primitive to make this circuit work. The module should output the AND of inputs a and b. The output port is already named c.

Try it yourself

module gate_challenge (
  input a,
  input b,
  output c
);
  
  // TODO: Add the correct gate primitive
  // The output c should be a AND b

endmodule