Recap - Logic Gate Circuit

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 42 of 90.

Challenge

This challenge combines everything you learned in this chapter about gate primitives. You will build a circuit using multiple gates.

What to do:

Build a circuit with:

Inputs: a, b, c
Outputs: out1, out2, out3

Logic:

out1 = a AND b
out2 = b OR c
out3 = a XOR c

Use gate primitives (and, or, xor) to create these outputs.

Try it yourself

module logic_circuit (
  input a,
  input b,
  input c,
  output out1,
  output out2,
  output out3
);
  
  // TODO: Add AND gate for out1 (a & b)
  
  // TODO: Add OR gate for out2 (b | c)
  
  // TODO: Add XOR gate for out3 (a ^ c)

endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Your First Module Comments Design Abstraction Levels

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR GatesRecap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

Practice on your own: Online Verilog compiler