Negative Numbers

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 16 of 90.

In Verilog, negative numbers are represented using two's complement format. Two's complement is a way to represent both positive and negative numbers in binary. The most significant bit (MSB) indicates the sign:

0 = positive number
1 = negative number

How to Calculate Two's Complement

To find the two's complement of a number:

Write the positive number in binary
Flip all bits (0 becomes 1, 1 becomes 0)
Add 1

Example: Represent -5 in 4 bits

Step	Operation	Result
1	Positive 5 in binary	0101
2	Flip all bits	1010
3	Add 1	1011

-5 in 4-bit two's complement is <strong>4'b1011</strong>

Writing Negative Numbers in Verilog

You can write negative numbers directly using decimal format:

reg signed [3:0] a;
a = -5;        // Verilog automatically uses two's complement

For sized binary numbers, you must write the two's complement value:

a = 4'b1011;   // This is -5 in 4-bit two's complement

Signed vs Unsigned

By default, Verilog treats numbers as unsigned. To work with negative numbers, declare signals as signed:

reg signed [3:0] negative;   // Can store -8 to 7
reg [3:0] positive;          // Can store 0 to 15

Range of Signed Numbers

For N bits, a signed number can represent:

Minimum: -2^(N-1)
Maximum: 2^(N-1) - 1

Bits	Range
4 bits	-8 to 7
8 bits	-128 to 127
16 bits	-32768 to 32767

Important Notes

Use signed keyword to enable negative number handling
Without signed, Verilog treats all values as positive

Two's complement arithmetic works automatically when using signed
The MSB determines sign: 1 = negative, 0 = positive

Challenge

Complete the code by writing the correct two's complement values.

What to do:

Set a to -3 using 4-bit two's complement binary
Set b to -8 using 4-bit two's complement binary
Set c to -1 using 4-bit two's complement binary

Try it yourself

module negative_challenge;
  reg signed [3:0] a, b, c;
  
  initial begin
    a = 4'b______;   // -3 in 4-bit two's complement
    b = 4'b______;   // -8 in 4-bit two's complement
    c = 4'b______;   // -1 in 4-bit two's complement
    
    $display("a = %d", a);
    $display("b = %d", b);
    $display("c = %d", c);
    $finish;
  end
endmodule