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Using Case Statement

Part of the Fundamentals section of Coddy's Verilog journey — lesson 66 of 90.

Challenge

Build a 4-to-1 multiplexer using a case statement instead of if-else.

Truth Table

sel	out
00	out = in0
01	out = in1
10	out = in2
11	out = in3

What to do:

Create a module named mux4to1_case
Add inputs in0, in1, in2, in3 (1 bit each)
Add input sel (2 bits)
Add output out (1 bit, type reg)
Add an always @(*) block
Inside, add a case (sel) statement
Add cases for 2'b00, 2'b01, 2'b10, 2'b11
Add a default case
Close with endcase and endmodule

Try it yourself

// TODO: Create module named mux4to1_case

// TODO: Add inputs: in0, in1, in2, in3 (1 bit each)

// TODO: Add input sel (2 bits)

// TODO: Add output out (reg type)

// TODO: Add always @(*) block

// TODO: Add case (sel)

// TODO: Add case 2'b00: out = in0;

// TODO: Add case 2'b01: out = in1;

// TODO: Add case 2'b10: out = in2;

// TODO: Add case 2'b11: out = in3;

// TODO: Add default: out = in0;

// TODO: Add endcase

// TODO: Add endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

3Number System

Binary Representation Sized Numbers Unsized Numbers Negative Numbers Special Values X And Z Recap - Number Formats

6Modules

Module Structure Input And Output Ports Inout Ports Module Instantiation Port Mapping By Name Port Mapping By Order Recap - Build A Module

9Procedural Blocks

Always Block Initial Block Sensitivity List Blocking Assignment Non Blocking Assignment Recap - Always vs Initial

12Multiplexer Project

2 To 1 Mux Design 4 To 1 Mux Design

Project lesson

Using Case Statement Project lesson

Project lesson

15Traffic Light Controller

Defining The States State Machine Logic

Project lesson

Timing The Transitions

Project lesson

Writing The Testbench

Project lesson

Verifying The Output

Project lesson