Conditional Operator
Part of the Fundamentals section of Coddy's Verilog journey — lesson 28 of 90.
The conditional operator ? : selects between two values based on a condition. It is also called the ternary operator. The conditional operator evaluates a condition and returns one of two values:
condition ? value_if_true : value_if_falseIf the condition is true (1), the first value is returned. If false (0), the second value is returned.
Why Use Conditional Operator
It is a compact way to write simple if-else logic in a single line. Common uses include:
- Selecting between two signals
- Creating multiplexers
- Setting default values
- Inline conditional assignments
Syntax and Examples
Basic example:
result = (a > b) ? a : b; // result gets the larger of a and bSelect between values:
data_out = (enable) ? data_in : 8'b00000000; // Output data if enabled, else 0Invert signal conditionally:
out = (invert) ? ~in : in; // If invert is 1, output inverted; else unchangedCode Example
module conditional_demo;
reg [3:0] a, b, max;
reg enable;
reg [3:0] data_in, data_out;
initial begin
a = 4'd7;
b = 4'd9;
enable = 1;
data_in = 4'b1010;
max = (a > b) ? a : b; // 9
data_out = (enable) ? data_in : 4'b0000; // 1010
$display("max = %d", max);
$display("data_out = %b", data_out);
$finish;
end
endmoduleOutput:
max = 9
data_out = 1010Nested Conditional Operators
You can nest conditional operators for multiple selections:
result = (a > b) ? a : (b > c) ? b : c; // Find the largest of three valuesUse parentheses to make nested conditions clear.
Important Notes
- The condition must be a single bit (or expression that evaluates to 0 or 1)
- Both value options must have the same bit width
- The operator can be used in continuous assignments (
assign) and procedural blocks (always,initial)
Challenge
Write the correct conditional expressions for each task.
What to do:
- Set
maxto the larger ofxandy - Set
absto the absolute value ofval(if negative, make positive) - Set
output_datatodataifenableis 1, otherwise to8'b0
Cheat sheet
The conditional (ternary) operator ? : selects between two values based on a condition:
condition ? value_if_true : value_if_falseExamples:
max = (a > b) ? a : b; // larger of a and b
data_out = (enable) ? data_in : 8'b0; // output data if enabled, else 0
out = (invert) ? ~in : in; // conditionally invert signalNested conditional operators:
result = (a > b) ? a : (b > c) ? b : c; // largest of three valuesNotes:
- Condition must evaluate to 0 or 1
- Both value options must have the same bit width
- Usable in
assign,always, andinitialblocks
Try it yourself
module conditional_challenge;
reg [3:0] x, y;
reg [3:0] max;
reg signed [3:0] val;
reg [3:0] abs;
reg enable;
reg [7:0] data;
reg [7:0] output_data;
initial begin
x = 4'd12;
y = 4'd8;
val = -4'sd5;
enable = 1;
data = 8'b10101010;
max = ______; // larger of x and y
abs = ______; // absolute value of val
output_data = ______; // data if enable, else 0
$display("max = %d", max);
$display("abs = %d", abs);
$display("output_data = %b", output_data);
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic