Wire Type

Part of the Fundamentals section of Coddy's Verilog journey — lesson 6 of 90.

In Verilog, we need to declare what type of signal we're using. The most common type is wire.

A wire represents a physical connection between components. It's like a real wire in a circuit.

Wires cannot store values - they just pass values through
Wires are used with assign statements
Wires are used to connect modules together

Declaring a Wire

wire a;           // Single-bit wire
wire b, c;        // Multiple wires on one line

How Wires Work

module wire_example;
  wire x;
  reg y;
  
  assign x = y;  // x always follows y
endmodule

x is connected to y. Whenever y changes, x changes instantly.

Wires are commonly used to connect inputs and outputs:

module and_gate(
  input a,      // 'a' is a wire by default
  input b,      // 'b' is a wire by default
  output c      // 'c' is a wire by default
);
  assign c = a & b;  // c is driven by this assignment
endmodule

In this example, a, b, and c are all wires.

Wires are the "glue" that connect different parts of your circuit together!

Challenge

What to do:

Add a wire called temp

Cheat sheet

Wire represents a physical connection between components. Wires cannot store values — they just pass values through.

wire a;       // Single-bit wire
wire b, c;    // Multiple wires on one line

Wires are used with assign statements. Whenever the source changes, the wire updates instantly:

wire x;
assign x = y;  // x always follows y

Module inputs and outputs are wires by default:

module and_gate(
  input a,   // wire by default
  input b,   // wire by default
  output c   // wire by default
);
  assign c = a & b;
endmodule

Try it yourself

module simple(
  input a,
  input b,
  output c
);

  assign c = a & b; 
  
  // Declare wire temp here 


endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register