Vectors

Part of the Fundamentals section of Coddy's Verilog journey — lesson 9 of 90.

A vector is a multi-bit wire or reg. Instead of a single bit, vectors let you work with buses of data. It is a collection of bits grouped together.

Note: A vector is not a separate data type. It is simply a multi-bit version of wire or reg.

wire single;        // Single bit
wire [7:0] bus;     // 8-bit vector (bits 7 down to 0)

In order to declare a vector, you use the syntax [MSB:LSB] where MSB is the most significant bit and LSB is the least significant.

wire [3:0] a;       // 4-bit wire vector
reg [7:0] data;     // 8-bit reg vector
wire [15:0] addr;   // 16-bit wire vector

Accessing Bits

When you access individual bits or slices of a vector, you use decimal numbers for the bit positions (indexes) and binary values (0 or 1) for the assignments.

This is because a bit position is a location (like an address), which is naturally expressed as a decimal number, while the value stored in that bit can only be 0 or 1 — a binary choice.

For example, data[0] means "bit number zero," and = 1 means "set it to high." You cannot assign a decimal like 75 to a single bit because a bit has no room for values other than 0 or 1.

reg [7:0] data;

data = 170;  
data[0] = 1;             // Set LSB to 1
data[7] = 0;             // Set MSB to 0
data[3:1] = 3'b101;      // Set bits 3,2,1 to 101 (binary remains)

Bit Order

The order of bits matters:

wire [3:0] a;     // a[3] is MSB, a[0] is LSB
wire [0:3] b;     // b[0] is MSB, b[3] is LSB (less common)

Most designers use [MSB:LSB] format with MSB on the left.

Assigning Values

reg [3:0] a;

a = 10;       
a = 5;         
a = 3;

Vector Slices

You can access a range of bits:

reg [15:0] word;

word[15:8] = 255;        // Assign upper byte (8'hFF = 255)
word[7:0]  = 0;          // Assign lower byte (8'h00 = 0)
word[3:1]  = 3'b101;     // Assign a slice

Challenge

The module below needs vector declarations.

What to do:

Change each input and output to be 8-bit vectors.

Cheat sheet

A vector is a multi-bit wire or reg, declared using [MSB:LSB] syntax:

wire [7:0] bus;     // 8-bit wire vector
reg [15:0] addr;    // 16-bit reg vector

Accessing individual bits and slices:

reg [7:0] data;

data[0] = 1;          // Set LSB to 1
data[7] = 0;          // Set MSB to 0
data[3:1] = 3'b101;   // Set bits 3,2,1 using binary

Bit order: [MSB:LSB] is the standard convention (e.g., [7:0] means bit 7 is MSB, bit 0 is LSB).

Try it yourself

module vector_example(
  input a,          // Change to 8-bit vector [7:0]
  input b,          // Change to 8-bit vector [7:0]
  output c          // Change to 8-bit vector [7:0]
);
  
  assign c = a & b;
  
endmodule