Sized Numbers

Part of the Fundamentals section of Coddy's Verilog journey — lesson 14 of 90.

There is a way to declare a number with a specific size in Verilog. It is called a sized number. It is useful because it prevents confusion about how many bits your number has and ensures your hardware behaves exactly as expected.

A sized number follows this format: [bits]'[format][value]

bits — the number of bits (for example, 8)
' — an apostrophe that separates the size from the format (required)

format — the base of the number: b for binary, d for decimal, h for hexadecimal, or o for octal
value — the actual number (for example, 1010)

For example:

4'b1010 — 4 bits, binary 1010 (decimal 10)
8'd255 — 8 bits, decimal 255 (binary 11111111)
16'hFF — 16 bits, hex FF (binary 0000000011111111)
3'b1 — 3 bits, binary 001 (the left bits are zero-filled)

Code Example:

reg [7:0] data;

data = 8'b10101010;   // 8 bits, binary 10101010
data = 8'd170;        // 8 bits, decimal 170
data = 8'hAA;         // 8 bits, hex AA

All three examples assign the same value to data.

Why Size Matters

Without size:

reg [7:0] data;
data = 1;        // What does this mean? 1 bit? 8 bits?

Verilog assumes small numbers are 32 bits by default, which can cause problems.

With size:

reg [7:0] data;
data = 8'b00000001;   // Clear: 8-bit value 1

Zero Padding

When you assign a smaller value to a larger vector, Verilog fills the left bits with zeros:

reg [7:0] data;
data = 4'b1010;    // Becomes 8'b00001010

Challenge

Complete the code by writing the correct sized numbers.

What to do:

Set a to an 8-bit binary number for decimal 170 (binary 10101010)
Set b to a 4-bit binary number for decimal 12 (binary 1100)
Set c to a 16-bit hex number for decimal 255 (hex FF)

Cheat sheet

A sized number in Verilog follows the format: [bits]'[format][value]

bits — number of bits
' — required apostrophe separator
format — b (binary), d (decimal), h (hex), o (octal)
value — the actual number

reg [7:0] data;

data = 8'b10101010;   // 8 bits, binary
data = 8'd170;        // 8 bits, decimal
data = 8'hAA;         // 8 bits, hex (all three are equal)

Without a size, Verilog defaults to 32 bits, which can cause unexpected behavior. Left bits are zero-padded when the value is smaller than the declared size:

reg [7:0] data;
data = 4'b1010;    // Becomes 8'b00001010

Try it yourself

module sized_challenge;
  reg [7:0] a;
  reg [3:0] b;
  reg [15:0] c;
  
  initial begin
    a = ______;   // 8-bit binary for 170 (10101010)
    b = ______;   // 4-bit binary for 12 (1100)
    c = ______;   // 16-bit hex for 255 (FF)
    
    $display("a = %b", a);
    $display("b = %b", b);
    $display("c = %h", c);
    $finish;
  end
endmodule