Disable Statement
Part of the Fundamentals section of Coddy's Verilog journey — lesson 62 of 90.
The disable statement stops the execution of a named block (like a forever loop, begin-end block, or task). It is useful for breaking out of loops that would otherwise run forever.
Syntax:
disable block_name;The block must be labeled with a name.
Disable with Forever Loop
begin : counter // counter gives the block the name counter.
forever begin
#10 count = count + 1;
if (count == 5) begin
disable counter; // disable counter stops that entire named block.
end
end
endThe forever loop is inside a named block counter. The disable counter statement is placed inside the loop. When count reaches 5, disable counter executes and stops the entire block counter — which immediately stops the forever loop as well.
Disable in a Separate Block
begin : counter
forever begin
#10 count = count + 1;
end
end
initial begin
#50;
disable counter; // Stops the counter block from outside
endHere, the forever loop runs continuously inside the named block counter. The disable counter statement is placed in a separate initial block. After 50 time units, disable counter executes and stops the counter block — which terminates the forever loop from the outside.
Important Rules
| Rule | Explanation |
|---|---|
| Block must be named | begin : block_name |
| Disable stops execution immediately | Code stops at that moment |
| Can be used from anywhere | From any block in the module |
Useful for stopping forever loops | Otherwise they never stop |
Challenge
You are given a module with a counter that runs forever.
What to do:
Complete the empty block by replacing each comment with the correct code:
- Add
#50;to wait 50 time units - Add
disable counter;to stop the counter block - Add
$display("Counter stopped");to print the message - Add
$finish;to end the simulation
Cheat sheet
The disable statement stops execution of a named block (e.g., forever loop). The block must be labeled using begin : block_name.
Disable from inside the block:
begin : counter
forever begin
#10 count = count + 1;
if (count == 5) disable counter;
end
endDisable from a separate block:
begin : counter
forever begin
#10 count = count + 1;
end
end
initial begin
#50;
disable counter; // stops the named block from outside
endTry it yourself
module disable_challenge;
integer count;
initial begin
count = 0;
fork
begin : counter
forever begin
#10 count = count + 1;
$display("count = %d", count);
end
end
begin
// Step 1: Wait 50 time units
// Step 2: Disable the counter block
// Step 3: Print "Counter stopped"
// Step 4: End the simulation
end
join
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic