Continuous Assignment

Part of the Fundamentals section of Coddy's Verilog journey — lesson 37 of 90.

In hardware, a connection is a physical wire that links two points in a circuit. Once the wire is in place, the connection is permanent and always active. If one end changes, the other end changes immediately.

In Verilog, we need a way to model this behavior. We want to pass a value onto a wire and keep it connected forever. The process of doing this is called continuous assignment.

Continuous assignment uses the assign keyword to create a permanent connection between a wire and an expression. The wire continuously takes the value of the expression — just like a physical wire.

Think of it as soldering a wire rather than writing a value once.

Syntax

assign wire_name = expression;

Part	Meaning
`assign`	Keyword that starts the continuous assignment
`wire_name`	The wire being driven (cannot be reg)
`expression`	The value that drives the wire

Simple Example

wire out;
assign out = a & b;

This means: out is always equal to a AND b. Whenever a or b changes, out changes immediately.

How It Works

Unlike a reg that stores a value, a wire with continuous assignment is constantly updated:

module continuous_demo;
  reg a, b;
  wire c;
  
  assign c = a & b;   // c follows a AND b at all times
  
  initial begin
    a = 0; b = 0;
    #10 $display("a=%d, b=%d, c=%d", a, b, c);  // c=0
    
    a = 1;
    #10 $display("a=%d, b=%d, c=%d", a, b, c);  // c=0 (1&0=0)
    
    b = 1;
    #10 $display("a=%d, b=%d, c=%d", a, b, c);  // c=1 (1&1=1)
    
    $finish;
  end
endmodule

Output:

a=0, b=0, c=0
a=1, b=0, c=0
a=1, b=1, c=1

Every time a or b changes, c updates automatically.

Multiple Assignments

You can have multiple continuous assignments in a module:

module multiple_assign (
  input a, b, c,
  output x, y
);
  assign x = a & b;
  assign y = x | c;   // y depends on x
endmodule

All assignments run in parallel, continuously.

Common Uses

Continuous assignments are used for:

Simple combinational logic (AND, OR, XOR)
Connecting wires together
Creating tri-state buffers
Driving outputs from combinational expressions

Challenge

What to do:

Add the missing continuous assignment that makes z equal to x AND y.

Cheat sheet

Continuous assignment creates a permanent connection between a wire and an expression using the assign keyword:

assign wire_name = expression;

The wire continuously reflects the expression's value — whenever inputs change, the output updates immediately:

wire out;
assign out = a & b; // out is always equal to a AND b

Multiple assignments run in parallel:

assign x = a & b;
assign y = x | c; // y depends on x, all update continuously

Key rules: only wire (not reg) can be driven by assign.

Try it yourself

module continuous_challenge (
  input x,
  input y,
  output z
);
  
  // TODO: Add the missing continuous assignment that makes z equal to x AND y
  

endmodule