Recap - Build A Module

Part of the Fundamentals section of Coddy's Verilog journey — lesson 36 of 90.

Challenge

This challenge combines everything you learned in this chapter. You will create a module from scratch and instantiate it.

What to do:

Part 1: Create a module called flipflop with:

1-bit input called clk
1-bit input called d
1-bit input called reset
1-bit output called q (use reg, assigned in always block)

The module should work as follows:

When reset is 1, q becomes 0
Otherwise, on each clock edge, q becomes d

Part 2: Instantiate the flipflop module in the top module using port mapping by name

Connect the ports to the following signals:

Port clk → signal clock
Port d → signal data
Port reset → signal reset_signal
Port q → signal out

Try it yourself

// Part 1: Create the flipflop module

  // TODO: Add ports

  // TODO: Add always block with posedge clk and posedge reset
  
  // If reset is 1, q <= 0
  
  // Else q <= d


// Part 2: Top module with instantiation
module top (
  input clock,
  input data,
  input reset_signal,
  output out
);

  // TODO: Instantiate flipflop with instance name ff1
  
  // Use port mapping by name: .clk(clock), .d(data), .reset(reset_signal), .q(out)

endmodule