Parameters
Part of the Fundamentals section of Coddy's Verilog journey. Lesson 11 of 90.
You can create many copies of the same module and use them in different places. This is called **multiple instances**. Instead of writing the same code again and again, you write it once and reuse it as many times as you need. Each instance is a separate copy of that hardware on the chip.
But what if you need each copy to be different? For example, one 8-bit counter, one 16-bit counter, and one 32-bit counter. Without parameters, you would need to write three separate modules.
Parameters solve this problem.
A parameter is a constant value that you can set when you create an instance. It lets you configure each copy of the module differently.
Declaring Parameters
module counter #(
parameter WIDTH = 8
)(
input clk,
output reg [WIDTH-1:0] count
);
always @(posedge clk) count <= count + 1;
endmoduleThe #(parameter WIDTH = 8) defines a parameter called WIDTH with a default value of 8.
While declaring parameters, we use the # symbol right after the module name and before the port list. The # tells Verilog that what follows is a list of parameters that configure the module. If your module has no parameters, you simply omit # entirely.
Using Parameters
Parameters can be used anywhere a constant is needed:
reg [WIDTH-1:0] data; // Vector size
count <= count + 1; // Works with any width
assign out = data[WIDTH-1]; // MSB positionOverriding Parameters
When you use the module, you can change the parameter value:
// Default width (8 bits)
counter u1 (.clk(clk), .reset(reset), .count(count1));
// Override to 16 bits
counter #(.WIDTH(16)) u2 (.clk(clk), .count(count2));Multiple Parameters
You can have multiple parameters:
module fifo #(
parameter DEPTH = 16,
parameter WIDTH = 8
)(
input clk, wr_en, rd_en,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out
);
reg [WIDTH-1:0] memory [0:DEPTH-1];
endmoduleLocalparam
A localparam is similar but cannot be overridden from outside:
module example;
localparam STATE_IDLE = 2'b00;
localparam STATE_RUN = 2'b01;
localparam STATE_STOP = 2'b10;
// These values are fixed inside this module
endmoduleUse localparam for constants that should not change.
Challenge
Add a parameter called WIDTH with a default value of 4.
What to do:
- Add a parameter named
WIDTH - Set its default value to
4 - The parameter goes inside
#( )after the module name
Try it yourself
module counter #(
// Add parameter WIDTH here with default 4
)(
input clk,
input reset,
output reg [WIDTH-1:0] count
);
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine LogicPractice on your own: Online Verilog compiler