Using System Tasks

Part of the Fundamentals section of Coddy's Verilog journey — lesson 77 of 90.

System tasks are built-in commands in Verilog that start with a dollar sign ($). They perform useful functions like printing messages, ending simulation, and creating waveform files.

We have already covered $display, $monitor, $dumpfile, and $dumpvars in previous lessons. In this lesson, we will look at additional system tasks that are useful in testbenches.

Additional System Tasks

System Task	Purpose
`$time`	Return current simulation time
`$finish`	End simulation
`$stop`	Pause simulation
`$random`	Generate random number

$time

Returns the current simulation time. Useful for tracking when events happen.

$display("Current time is %0t", $time);

$finish

Ends the simulation. Always use at the end of your testbench.

$finish;

$stop

Pauses the simulation. Can be resumed with a simulator command. Useful for debugging.

$stop;

$random

Generates a random number. Useful for creating random test stimulus.

reg [7:0] rand_value;
rand_value = $random;

Example Using Multiple System Tasks

module system_tasks_demo;
  reg [7:0] data;
  integer i;
  
  initial begin
    $display("Simulation started at time %0t", $time);
    
    for (i = 0; i < 5; i = i + 1) begin
      data = $random;
      $display("Random value %d: %b", i, data);
    end
    
    $stop;
    #10 $display("Resumed at time %0t", $time);
    
    $display("Simulation finished at time %0t", $time);
    $finish;
  end
endmodule

Challenge

Add the missing system tasks to this testbench.

What to do:

Add $display to print current time at the start
Add $display to print current time at the end
Add $finish to end the simulation

Cheat sheet

System tasks in Verilog start with $ and perform simulation utilities:

System Task	Purpose
`$time`	Return current simulation time
`$finish`	End simulation
`$stop`	Pause simulation
`$random`	Generate random number

$display("Time: %0t", $time); // print current time
$finish;                       // end simulation
$stop;                         // pause simulation

reg [7:0] rand_value;
rand_value = $random;          // assign random number

Try it yourself

module and_gate (
  input a,
  input b,
  output c
);
  assign c = a & b;
endmodule

module testbench;
  reg a, b;
  wire c;
  
  and_gate dut (
    .a(a),
    .b(b),
    .c(c)
  );

  initial begin
    // TODO: Add $display with current time at start
    // Format: "Start time: %0t"
    
    
    $monitor("Time %0t: a=%b, b=%b, c=%b", $time, a, b, c);
    
    a = 0; b = 0; #10;
    a = 0; b = 1; #10;
    a = 1; b = 0; #10;
    a = 1; b = 1; #10;
    
    // TODO: Add $display with current time at end
    // Format: "End time: %0t"
    
    
    // TODO: Add $finish
    
  end
endmodule