Timescale Directive
Part of the Fundamentals section of Coddy's Verilog journey. Lesson 70 of 90.
The timescale directive sets the time unit and time precision for simulation. It tells the simulator how to interpret delay values like #10.
In previous lessons, we used delays like #10 without specifying what "10" means. Is it 10 nanoseconds? 10 picoseconds? The timescale directive answers this question.
Syntax:
`timescale time_unit / time_precision| Part | Meaning | Example |
|---|---|---|
time_unit | The basic unit for delays | 1ns |
time_precision | How precise simulation should be | 1ps |
The backtick ` before timescale means it is a compiler directive.
Example
`timescale 1ns / 1pstime_unit = 1ns→#10means 10 nanosecondstime_precision = 1ps→ Simulation rounds to the nearest picosecond
Common Timescale Values
| Time Unit | Precision | Use Case |
|---|---|---|
1ns / 1ns | Nanosecond | Simple simulations |
1ns / 1ps | Picosecond | More precise |
1ps / 1ps | Picosecond | High-speed designs |
1us / 1ns | Microsecond | Slow simulations |
How It Affects Delays
`timescale 1ns / 1ps
initial begin
#10 a = 1; // Waits 10 nanoseconds
endWithout timescale, some simulators assume a default (often 1ns). It is best to always specify it.
Important Rules
| Rule | Explanation |
|---|---|
| Must be outside modules | Placed before any module definition |
| Backtick symbol | `timescale not 'timescale |
| Time unit ≥ time precision | 1ns / 1ps is fine, 1ps / 1ns is not |
| Affects all delays in the file | General delays, gate delays, assignment delays |
Challenge
What to do:
Add the missing timescale directive to make the delays represent 10ns, 20ns, and 30ns.
Try it yourself
// TODO: Add timescale directive (1ns / 1ps)
module timescale_challenge;
initial begin
$display("Time %0t", $time);
#10 $display("Time %0t (10ns = 10000ps)", $time);
#10 $display("Time %0t (20ns = 20000ps)", $time);
#10 $display("Time %0t (30ns = 30000ps)", $time);
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design13Timing And Delays
What Are DelaysGate DelaysAssignment DelaysTimescale DirectiveClock GenerationRecap - Timing Control5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine LogicPractice on your own: Online Verilog compiler