Writing The Module

Part of the Fundamentals section of Coddy's Verilog journey — lesson 43 of 90.

Challenge

A half adder is a circuit that adds two single bits and tells you:

sum — the result (0 or 1)
carry — if there is an overflow (1 when both inputs are 1)

Example

a	b	sum	carry
0	0	0	no overflow
0	1	1	no overflow
1	0	1	no overflow
1	1	0	overflow (carry = 1)

When you add 1 + 1 in binary, the result is 0 with a carry of 1 (just like 5 + 5 = 0 with a carry of 1 in decimal).

Before we add the logic, we need to create the module container — the empty shell that will hold our half adder circuit.

For a half adder, these are the tasks:

Create a module called half_adder
Add two inputs: a and b
Add two outputs: sum and carry

Try it yourself

  // Task 1: Create a module named half_adder

  // Task 2: Add two inputs: a and b
  
  // Task 3: Add two outputs: sum and carry

  // Logic will be added later

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays Parameters Recap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The ModuleDesigning The Logic

Writing The Testbench

11Loops

For Loop While Loop Repeat Loop Forever Loop Disable Statement Recap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counter State Machine

Transmitter Design

Testbench