Menu
Coddy logo textTech

Repeat Loop

Part of the Fundamentals section of Coddy's Verilog journey — lesson 60 of 90.

The repeat loop executes a block of code a fixed number of times. Unlike the for loop, it does not use a loop counter variable.

A repeat loop runs a specified number of times. You give it a constant or expression that determines how many iterations to execute.

Syntax:

repeat (number) begin
  // Code to repeat
end

Simple Example

repeat (5) begin
  $display("Hello");
end

Output:

Hello
Hello
Hello
Hello
Hello

The message prints exactly 5 times.

Repeat with an Expression

integer count = 3;

repeat (count) begin
  $display("Looping");
end

Output:

Looping
Looping
Looping

Repeat vs For Loop

 For LoopRepeat Loop
Counter variableYes (explicit)No
When to useNeed index valueJust need repetition
Examplefor (i=0; i<5; i=i+1)repeat (5)

Generating Multiple Clock Cycles

initial begin
  clk = 0;
  repeat (20) begin
    #5 clk = ~clk;
  end
end

This generates 20 clock edges (10 complete cycles).

Important Rules

RuleExplanation
Number must be non-negativeCannot repeat negative times
Can use constant or expressionrepeat (10) or repeat (count)
No loop variable availableCannot track iteration number
Use begin/end for multiple statementsRequired for more than one line
challenge icon

Challenge

What to do:

Add the missing repeat loop to print "Verilog" 4 times.

Cheat sheet

The repeat loop executes a block of code a fixed number of times without a loop counter variable.

repeat (number) begin
  // Code to repeat
end

Can use a constant or variable expression:

integer count = 3;
repeat (count) begin
  $display("Looping");
end

Common use case — generating clock cycles:

repeat (20) begin
  #5 clk = ~clk;
end

Repeat vs For Loop: Use repeat when you only need repetition (no index needed); use for when you need the iteration counter value.

Try it yourself

module repeat_challenge;
  
  initial begin
    $display("Printing 4 times:");
    
    // TODO: Add repeat loop
    // Repeat 4 times
    // Inside, print "Verilog"
    
    $finish;
  end
endmodule
quiz iconTest yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in Fundamentals