If Statement

Part of the Fundamentals section of Coddy's Verilog journey — lesson 52 of 90.

The if statement is a decision-making block that executes code only when a condition is true. The if statement checks a condition.

If the condition is true (1), the code inside executes. If the condition is false (0), the code is skipped.

Syntax:

if (condition) begin
  // Code executes when condition is true
end

Simple Example

if (reset) begin
  count = 0;
end

In this example:

begin and end are used to mark the start and end of the code block

If reset is 1 (true), the code inside begin and end executes → count becomes 0
If reset is 0 (false), the code inside is skipped → nothing happens

begin and end work like curly braces { } in other programming languages. They group statements together so Verilog knows which code belongs to the if condition. Even though there is only one statement here, using begin and end is still good practice for consistency.

If Statement in Always Block

always @(posedge clk) begin
  if (reset)
    count <= 0;
end

Note: For a single statement, begin and end are optional. For example, in the always block above no begin/end is needed after if because it has only one statement.

Condition Can Be Any Expression

if (a > b) begin
  max = a;
end

if (a && b) begin
  out = 1;
end

if (data == 8'hFF) begin
  match = 1;
end

Important Rules

Rule	Explanation
Condition must be a single bit	Or expression that evaluates to 0 or 1
`begin` / `end` needed for multiple statements	Like `{ }` in other languages
Without `begin`/`end`, only one statement follows	The next line only

Challenge

What to do:

Add the missing if statement to make this work.

When enable is 1, out should equal a & b
When enable is 0, out should remain 0 (not change)

The starter code initializes out = 0 and tests both cases.

Cheat sheet

The if statement executes code only when a condition is true (1), and skips it when false (0).

if (condition) begin
  // executes when condition is true
end

For a single statement, begin/end are optional:

always @(posedge clk) begin
  if (reset)
    count <= 0;
end

Conditions can be any expression evaluating to 0 or 1:

if (a > b) begin max = a; end
if (a && b) begin out = 1; end
if (data == 8'hFF) begin match = 1; end

Key rules:

Use begin/end to group multiple statements (like { } in other languages)
Without begin/end, only the immediately following line belongs to the if

Try it yourself

module if_challenge;
  reg a, b, enable;
  reg out = 0;
  
  initial begin
    a = 1;
    b = 1;
    
    // Test case 1: enable = 1
    enable = 1;
    // TODO: Add if statement (out = a & b)
    $display("enable=1: out = %d (should be 1)", out);
    
    // Test case 2: enable = 0
    enable = 0;
    out = 0; 
    // TODO: out should stay 0
    $display("enable=0: out = %d (should be 0)", out);
    
    $finish;
  end
endmodule