Creating Stimulus

Part of the Fundamentals section of Coddy's Verilog journey — lesson 74 of 90.

Stimulus refers to the input values you apply to your design to test if it works correctly. By changing the inputs and observing the outputs, you can verify that your design behaves as expected.

Think of it like testing a machine: you press different buttons (stimulus) and watch what happens (outputs). Creating good stimulus is an essential part of writing a testbench.

For example, look at the stimulus in the following testbench:

module testbench;
  reg a, b;
  wire c;
  
  and_gate dut (
    .a(a),
    .b(b),
    .c(c)
  );

  initial begin
    // STIMULUS STARTS HERE
    
    // Test case 1: Both inputs are 0
    a = 0; b = 0; #10;
    
    // Test case 2: a=0, b=1
    a = 0; b = 1; #10;
    
    // Test case 3: a=1, b=0
    a = 1; b = 0; #10;
    
    // Test case 4: Both inputs are 1
    a = 1; b = 1; #10;

    // STIMULUS ENDS HERE
    
    $finish;
  end
endmodule

Each stimulus is applied, then we wait 10 time units (#10) before the next stimulus. This gives the DUT time to produce an output.

Methods to Create Stimulus

Method	Best For	Example
Sequential assignments	Simple tests	`a = 0; b = 0; #10;`
For loop	Testing all combinations	`for (i = 0; i < 4; i++)`
Repeat loop	Repeating patterns	`repeat (10) #5 clk = ~clk;`
Forever loop	Continuous signals	`forever #5 clk = ~clk;`

Method 1: Sequential Assignments

The simplest way to create stimulus. You assign values one by one with delays.

initial begin
  a = 0; b = 0; #10;
  a = 0; b = 1; #10;
  a = 1; b = 0; #10;
  a = 1; b = 1; #10;
  $finish;
end

Method 2: For Loop

Useful when you want to test all possible input combinations.

integer i;

initial begin
  for (i = 0; i < 4; i = i + 1) begin
    {a, b} = i;
    #10;
  end
  $finish;
end

This tests: 00, 01, 10, 11.

Method 3: Repeat Loop

Useful for repeating the same stimulus many times.

initial begin
  a = 0; b = 1;
  repeat (10) begin
    #10 a = ~a;
  end
  $finish;
end

Method 4: Forever Loop

Useful for continuous signals like clocks.

initial begin
  clk = 0;
  forever #5 clk = ~clk;
end

Important Rules

Rule	Explanation
Use delays between stimulus assignments	`#10` allows time for DUT to respond
Use `reg` for stimulus signals	Because they change over time
Add `$finish` at the end	To stop simulation

Challenge

You are given an OR gate module. Your task is to add the missing stimulus and $display statements to print the results.

What to do:

Add stimulus to test all four input combinations (00, 01, 10, 11):

On each line, set the values for x and y
Add #10 for a delay
Add $display to print the result

The <strong>$display</strong> should look like this:

$display("%d %d | %d", x, y, z);

Cheat sheet

Stimulus is the input values applied to a DUT in a testbench to verify correct behavior.

Methods to Create Stimulus

Sequential assignments – simplest approach:

initial begin
  a = 0; b = 0; #10;
  a = 0; b = 1; #10;
  $finish;
end

For loop – test all input combinations:

integer i;
initial begin
  for (i = 0; i < 4; i = i + 1) begin
    {a, b} = i; #10;
  end
  $finish;
end

Repeat loop – repeat stimulus N times:

repeat (10) begin
  #10 a = ~a;
end

Forever loop – continuous signals like clocks:

initial begin
  clk = 0;
  forever #5 clk = ~clk;
end

Key Rules

Use reg for stimulus signals (they change over time)
Add delays (e.g. #10) between assignments to allow DUT to respond
End simulation with $finish

Try it yourself

module or_gate (
  input x,
  input y,
  output z
);
  assign z = x | y;
endmodule

module testbench;
  reg x, y;
  wire z;
  
  or_gate dut (
    .x(x),
    .y(y),
    .z(z)
  );

  initial begin
    $display("x y | z");
    $display("---------");
    
    // TODO: Add stimulus and display for 0 0
    
    // TODO: Add stimulus and display for 0 1
    
    // TODO: Add stimulus and display for 1 0
    
    // TODO: Add stimulus and display for 1 1
    
    $finish;
  end
endmodule