Always Block

Part of the Fundamentals section of Coddy's Verilog journey — lesson 46 of 90.

A procedural block is a block of code where statements execute one after another, in sequence — just like in software programming languages like C or Python. Verilog has two procedural blocks: initial (runs once) and always (runs continuously). Let's start with the always block.

The always block runs continuously — it repeats forever once the simulation starts. It is used to describe hardware that needs to keep running, such as flip-flops, counters, and combinational logic.

Basic syntax:

always @(sensitivity_list) begin
  // Code that runs repeatedly
end

The @(sensitivity_list) tells the block when to execute. Without it, the block would loop infinitely and hang the simulation.

Always Block Example: Counter

Here is an example of how we can use the always block to create a counter.

module counter (
  input clk,
  output reg [3:0] count
);
  always @(posedge clk) count = count + 1;
endmodule

How This Code Works

Part	Meaning
`always`	Run this code repeatedly, forever
`@(posedge clk)`	Wait for the clock to go from 0 to 1 (rising edge)
`count = count + 1`	Take the current value of `count`, add 1, and store it back

The block runs on every rising edge of the clock. Each time, count increases by 1.

The sensitivity list @(posedge clk) tells it to execute only on clock edges, not continuously. Without this, the loop would run forever with no delay.

Always Block with Multiple Signals

You can list specific signals:

always @(a or b) begin
  out = a & b;
end

This runs when a or b changes.

Challenge

Add the missing always block to make this module work.

How it works:

On each rising clock edge, out1 toggles (flips) from 0 to 1 or 1 to 0
out2 follows out1 (same value as out1)

What to do:

Add an always @(posedge clk) block
Inside, make out1 toggle (use out1 = ~out1)
Make out2 equal to out1

Cheat sheet

The always block runs continuously and is used to describe hardware like flip-flops and counters.

always @(sensitivity_list) begin
  // Code that runs repeatedly
end

@(posedge clk) triggers on the rising clock edge; @(a or b) triggers when any listed signal changes.

// Counter: increments on every rising clock edge
always @(posedge clk) count = count + 1;

// Combinational: runs when a or b changes
always @(a or b) begin
  out = a & b;
end

Note: outputs driven by always blocks must be declared as reg.

Try it yourself

module toggler (
  input clk,
  output reg out1,
  output reg out2
);

  initial begin
    out1 = 0;
    out2 = 0;
  end

  // TODO: Add always block with posedge clk
  // out1 toggles every clock
  // out2 follows out1

endmodule