Recap - ALU Design

Part of the Fundamentals section of Coddy's Verilog journey — lesson 57 of 90.

Challenge

An ALU (Arithmetic Logic Unit) is a digital circuit that takes two inputs, performs an operation on them, and produces one output. It performs arithmetic and logic operations on two inputs based on a select signal. The select signal chooses one operation to execute.

How it works

select	Operation	Output
`2'b00`	Addition	`a + b`
`2'b01`	Subtraction	`a - b`
`2'b10`	Bitwise AND	`a & b`
`2'b11`	Bitwise OR	`a \| b`

Build a simple ALU using a `case` statement.

What to do:

Create a module named alu
Add inputs: a (4-bit), b (4-bit), select (2-bit)
Add output: result (4-bit, reg type)
Add an always @(*) block
Inside, add a case (select) statement
Add four cases for 2'b00, 2'b01, 2'b10, 2'b11
Add a default case to set result = 0
Close with endcase and endmodule

Try it yourself

// TODO: Create module alu 

  // TODO: Add inputs (a, b, select)
  
  // TODO: Add output (result)

  // TODO: Add always @(*) block
  
  // TODO: Add case (select)
  
  // TODO: Add case 2'b00: result = a + b;
  
  // TODO: Add case 2'b01: result = a - b;
  
  // TODO: Add case 2'b10: result = a & b;
  
  // TODO: Add case 2'b11: result = a | b;
  
  // TODO: Add default: result = 0;
  
  // TODO: Add endcase

// TODO: Add endmodule