Comparison Operators
Part of the Fundamentals section of Coddy's Verilog journey — lesson 21 of 90.
Comparison operators compare two values and return either 1 (true) or 0 (false).
Available Comparison Operators
| Operator | Meaning |
|---|---|
== | Equal to |
!= | Not equal to |
> | Greater than |
< | Less than |
>= | Greater than or equal |
<= | Less than or equal |
Code Example
module comparison_demo;
reg [3:0] a, b;
reg result;
initial begin
a = 5;
b = 3;
result = (a == b);
$display("5 == 3 : %d", result); // 0 (false)
result = (a != b);
$display("5 != 3 : %d", result); // 1 (true)
result = (a > b);
$display("5 > 3 : %d", result); // 1 (true)
result = (a < b);
$display("5 < 3 : %d", result); // 0 (false)
result = (a >= 5);
$display("5 >= 5 : %d", result); // 1 (true)
result = (a <= 3);
$display("5 <= 3 : %d", result); // 0 (false)
$finish;
end
endmoduleOutput:
5 == 3 : 0
5 != 3 : 1
5 > 3 : 1
5 < 3 : 0
5 >= 5 : 1
5 <= 3 : 0Using Comparisons in Conditions
Comparisons are often used in if statements:
if (count == 10)
$display("Reached maximum");
if (value > threshold)
$display("Value is too high");Important Notes
- Comparison results are 1-bit values (0 or 1)
- Comparisons work with any bit width
- Be careful with
==and!=when signals contain X or Z (they will return X)
Challenge
Write the correct comparison expressions for each task.
What to do:
- Check if
aequalsband store ineq - Check if
ais greater thanband store ingt - Check if
ais less than or equal toband store inle
Cheat sheet
Comparison operators in Verilog compare two values and return 1 (true) or 0 (false).
| Operator | Meaning |
|---|---|
== | Equal to |
!= | Not equal to |
> | Greater than |
< | Less than |
>= | Greater than or equal |
<= | Less than or equal |
Comparisons are commonly used in if statements:
if (count == 10)
$display("Reached maximum");
if (value > threshold)
$display("Value is too high");Note: Results are 1-bit values. Using == or != with signals containing X or Z will return X.
Try it yourself
module comparison_challenge;
reg [3:0] a, b;
reg eq, gt, le;
initial begin
a = 4'd7;
b = 4'd7;
eq = ______; // a equals b
gt = ______; // a greater than b
le = ______; // a less than or equal to b
$display("a = %d, b = %d", a, b);
$display("a == b : %d", eq);
$display("a > b : %d", gt);
$display("a <= b : %d", le);
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic