Assign With Operators

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 38 of 90.

Once you understand continuous assignment, you can combine it with operators to create useful logic. The assign statement can use any operator to drive a wire.

Basic Syntax

assign wire_name = expression;

The expression can include:

Arithmetic operators (+, -, *, /)
Bitwise operators (&, |, ^, ~)
Logical operators (&&, ||, !)

Comparison operators (>, <, ==, !=)
Shift operators (<<, >>)
Conditional operator (? :)

Examples with Different Operators

Bitwise AND:

assign out = a & b;

Addition:

assign sum = a + b;

Comparison:

assign is_greater = (a > b);

Conditional (multiplexer):

assign out = sel ? a : b;

Shift:

assign shifted = data << 2;

Concatenation:

assign bus = {high_byte, low_byte};

Code Example

module assign_operators (
  input [3:0] a, b,
  input sel,
  output [3:0] and_out,
  output [4:0] sum_out,
  output is_equal,
  output mux_out
);
  
  assign and_out = a & b;           // Bitwise AND
  assign sum_out = a + b;           // Addition
  assign is_equal = (a == b);       // Comparison
  assign mux_out = sel ? a : b;     // Conditional (multiplexer)
  
endmodule

Multiple Operators in One Assignment

You can combine operators in a single expression:

assign result = (a & b) | (c ^ d);
assign final = (a + b) > (c - d);
assign parity = ^data;   // Reduction XOR (odd number of 1's)

Operator Precedence

Verilog follows standard operator precedence. Use parentheses ( ) to make your intention clear:

// Unclear
assign out = a & b | c;

// Clear
assign out = (a & b) | c;

Challenge

Add the missing assign statements based on the tasks.

What to do:

Make and_result equal to input_a AND input_b (bitwise)
Make or_result equal to input_a OR input_b (bitwise)
Make xor_result equal to input_a XOR input_b (bitwise)
Make not_result equal to NOT input_a (bitwise)

Try it yourself

module assign_challenge (
  input input_a,
  input input_b,
  output and_result,
  output or_result,
  output xor_result,
  output not_result
);
  
  // TODO: Add assign statements for:
  // and_result = input_a & input_b
  // or_result  = input_a | input_b
  // xor_result = input_a ^ input_b
  // not_result = ~input_a

endmodule