Gate Delays

Part of the Fundamentals section of Coddy's Verilog journey — lesson 68 of 90.

In the previous lesson, we covered general delays used like #10 a = b; — they wait before executing a statement.

In this lesson, we cover gate delays, which are specific to built-in gate primitives like and, or, and not. A gate delay models how long a hardware gate takes to produce an output after its inputs change.

In real hardware, gates do not respond instantly — there is a small delay. When you use built-in gate primitives, you can add a delay to simulate the gate's propagation time. The output changes only after the specified delay.

Difference Between General Delay and Gate Delay

	General Delay	Gate Delay
Syntax	`#10 a = b;`	`and #5 (out, a, b);`
Position	`#` before a statement	`#` inside gate primitive
Purpose	Wait before executing	Model gate propagation time

Syntax:

gate_type #(delay) (output, input1, input2, ...);

The #(delay) specifies how many time units the gate takes to respond.

Simple Example

and #5 (out, a, b);

This AND gate takes 5 time units to change its output after a or b changes.

Gate Delay with Multiple Inputs

nand #8 (out, a, b, c, d);   // 4-input NAND with 8 time unit delay

Important Rules

Rule	Explanation
Delay comes after gate name	`and #5 (out, a, b)`
Delay value in time units	Based on `timescale` directive
All inputs affect output	Any input change triggers the delay
Not synthesizable	Gate delays are for simulation only

Challenge

Add the missing gate delays to this module. Use different delays for each gate.

What to do:

AND gate: 5 time unit delay
OR gate: 3 time unit delay
NOT gate: 2 time unit delay

Cheat sheet

Gate delays model propagation time in built-in gate primitives.

Syntax:

gate_type #(delay) (output, input1, input2, ...);

Examples:

and  #5 (out, a, b);         // AND gate, 5 time unit delay
or   #3 (out, a, b);         // OR gate, 3 time unit delay
not  #2 (out, a);            // NOT gate, 2 time unit delay
nand #8 (out, a, b, c, d);   // 4-input NAND, 8 time unit delay

Key points:

# comes after the gate name, before the port list
Any input change triggers the delay before output updates
Gate delays are for simulation only — not synthesizable

Try it yourself

module gate_delay_challenge;
  reg a, b;
  wire and_out, or_out, not_out;
  
  // TODO: Add AND gate with 5 time unit delay (inputs a, b)
  
  // TODO: Add OR gate with 3 time unit delay (inputs a, b)
  
  // TODO: Add NOT gate with 2 time unit delay (input a)
  

  initial begin
    $monitor("Time %0t: a=%b, b=%b | and=%b, or=%b, not=%b", 
              $time, a, b, and_out, or_out, not_out);
    
    a = 1; b = 1;
    #10 $finish;
  end
endmodule