Shift Register

Part of the Fundamentals section of Coddy's Verilog journey — lesson 86 of 90.

Challenge

A shift register shifts data from left to right on each clock edge. Each bit moves to the next position.

How a 4-bit Shift Register Works

Initial: q0=0, q1=0, q2=0, q3=0
Clock 1: q0 = d, q1 = old q0, q2 = old q1, q3 = old q2
Clock 2: q0 = d, q1 = old q0, q2 = old q1, q3 = old q2

After 4 clock cycles, the first input bit reaches q3.

Module Interface

Port	Direction	Width	Description
`clk`	input	1 bit	Clock signal
`reset`	input	1 bit	Reset all outputs to 0
`d`	input	1 bit	Data input
`q0`	output	1 bit	First flip-flop output
`q1`	output	1 bit	Second flip-flop output
`q2`	output	1 bit	Third flip-flop output
`q3`	output	1 bit	Fourth flip-flop output

Your task is to complete the module below.

What to do:

On reset, set all outputs to 0
On each rising clock edge, shift data from left to right:
1. q0 gets d
2. q1 gets old q0
3. q2 gets old q1
4. q3 gets old q2

Try it yourself

module shift_register (
  input clk,
  input reset,
  input d,
  output reg q0,
  output reg q1,
  output reg q2,
  output reg q3
);
  
  // TODO: Add always @(posedge clk or posedge reset)
  // On reset: q0<=0, q1<=0, q2<=0, q3<=0
  // Else: shift data: q0 <= d, q1 <= q0, q2 <= q1, q3 <= q2

endmodule