4 Bit Counter

Part of the Fundamentals section of Coddy's Verilog journey — lesson 84 of 90.

Challenge

Build a 4-bit counter that counts from 0 to 15 and wraps back to 0.

Module Interface

Port	Direction	Width	Description
`clk`	input	1 bit	Clock signal
`reset`	input	1 bit	Reset counter to 0
`count`	output	4 bits	Current counter value

Truth Table

Clock Cycle	count
After reset	0
1	1
2	2
...	...
15	15
16	0 (wraps around)

Your task is to complete the module below.

What to do:

On reset, set count to 0
On each rising clock edge, increment count by 1
When count reaches 15, the next increment should wrap to 0

Try it yourself

module counter (
  input clk,
  input reset,
  output reg [3:0] count
);
  
  // TODO: Add always block with posedge clk and posedge reset
  // On reset: count <= 0
  // Otherwise: count <= count + 1

endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit CounterDecoder Design Shift Register