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State Machine

Part of the Fundamentals section of Coddy's Verilog journey — lesson 88 of 90.

Challenge

A state machine is a circuit that can be in one of several states. For UART, we have different states for each bit: idle, start, data bits 0-7, and stop. The bit counter (cnt) tells us which state we are in. Based on cnt, we decide what value to send on the tx line.

You have the bit counter from the previous lesson. You need to modify it to work as a UART transmitter.

Bit Values to Send (for letter 'A')

cnt	tx value
0	1
1	0
2	1
3	0
4	0
5	0
6	0
7	0
8	0
9	1
10	1

What to do

Add an input called start
Add an output reg called tx
In the initial block, set tx = 1 (idle high)
Change the counter logic:
- When cnt == 0 and start == 1, set cnt <= 1 (start transmitting)
- When cnt is between 1 and 9, increment: cnt <= cnt + 1
- When cnt == 10, reset to 0

Try it yourself

module uart_tx (
  input clk,
  output reg [3:0] cnt
);

  initial begin
    cnt = 0;
  end

  always @(posedge clk) begin
      cnt <= cnt + 1;
  end

endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays Parameters Recap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The Module Designing The Logic

Project lesson

Writing The Testbench

Project lesson

11Loops

For Loop While Loop Repeat Loop Forever Loop Disable Statement Recap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counterState Machine Project lesson

Project lesson

Transmitter Design

Project lesson

Project lesson