Case Statement

Part of the Fundamentals section of Coddy's Verilog journey — lesson 55 of 90.

The case statement allows you to choose between many different actions based on the value of a single expression. It is a cleaner alternative to multiple if-else statements when comparing the same variable to many different values.

The case statement compares an expression to a list of values and executes the matching block. It is like a multi-way branch.

Syntax:

case (expression)
  value1: statement1;
  value2: statement2;
  default: default_statement;
endcase

It is strongly recommended to always include <strong>default</strong> in a combinational <strong>case</strong> statement. Without default, if sel takes an unexpected value (like X or Z), out will not be assigned and will latch its previous value. This creates unintended memory (a latch) instead of pure combinational logic.

Simple Example

case (sel)
  2'b00: out = a;
  2'b01: out = b;
  2'b10: out = c;
  default: out = 0;
endcase

If sel is 00, out gets a. If sel is 01, out gets b. If sel is 10, out gets c.

Otherwise, out gets 0.

Multiple Statements per Case

Use begin and end for multiple statements:

case (state)
  2'b00: begin
    out = a;
    flag = 1;
  end
  2'b01: begin
    out = b;
    flag = 0;
  end
  default: out = 0;
endcase

Important Rules

Rule	Explanation
All case values must be unique	No duplicate values
Values must match bit width	`2'b01` not `1'b1`
`default` is optional but recommended	Catches unmapped values
Without `default`, unmapped values cause latches	In combinational logic

Case vs If-Else

	Case	If-Else
Best for	One variable, many values	Complex conditions
Readability	Very clear	Can get messy
Example	Multiplexer, decoder	Comparator, range checks

Challenge

Complete the Case Statement

What to do:

Add the missing case statement to make this multiplexer work.

How it works:

When select = 2'b00, result = in0
When select = 2'b01, result = in1
When select = 2'b10, result = in2
When select = 2'b11, result = in3

Cheat sheet

The case statement selects between multiple actions based on a single expression — a cleaner alternative to chained if-else.

case (expression)
  value1: statement1;
  value2: statement2;
  default: default_statement;
endcase

For multiple statements per branch, use begin/end:

case (sel)
  2'b00: out = a;
  2'b01: begin
    out = b;
    flag = 1;
  end
  default: out = 0;
endcase

Always include default in combinational logic. Without it, unmatched values (e.g., X, Z) cause the output to retain its previous value, creating an unintended latch.

Key rules:

All case values must be unique
Values must match the expression's bit width (e.g., 2'b01, not 1'b1)
Use case for one variable vs. many values; use if-else for complex/range conditions

Try it yourself

module mux4 (
  input [1:0] select,
  input in0, in1, in2, in3,
  output reg result
);
  
  always @(*) begin
    // TODO: Add case statement
    // select=00 -> result = in0
    // select=01 -> result = in1
    // select=10 -> result = in2
    // select=11 -> result = in3
    // default -> result = 0
  end
  
endmodule