Sensitivity List

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 48 of 90.

The sensitivity list tells the always block when to execute. It is written inside parentheses after the @ symbol.

The sensitivity list is a set of signals or events that trigger the always block. When any signal in the list changes, the block executes.

Syntax:

always @(sensitivity_list) begin
  // Code runs when signals in the list change
end

Types of Sensitivity List

Type	Syntax	When Block Executes
All signals (combinational)	`always @(*)`	When any signal inside changes
Specific signals	`always @(a or b)`	When `a` or `b` changes
Edge trigger (sequential)	`always @(posedge clk)`	On rising edge of clock
Multiple edges	`always @(posedge clk or posedge reset)`	On clock edge or reset edge

Option 1: All Signals `(*)`

The safest and most common for combinational logic.

always @(*) begin
  out = a & b;   // Runs when a or b changes
end

The * automatically includes all signals read in the block.

Option 2: Specific Signals

always @(a or b) begin
  out = a & b;   // Runs when a or b changes
end

If you forget a signal, the output does not update in simulation when that signal changes, so the simulation no longer matches the synthesized hardware.

Option 3: Edge Trigger (posedge)

always @(posedge clk) begin
  q <= d;        // Runs on rising edge of clock
end

Use posedge for rising edge, negedge for falling edge.

Option 4: Multiple Edges

always @(posedge clk or posedge reset) begin
  if (reset)
    q <= 0;
  else
    q <= d;
end

Runs on clock edge or reset edge.

Common Mistakes

Mistake	Why Wrong
`always @(a or b or c)` but uses `d`	Missing `d` → output goes stale in simulation (sim/synth mismatch)
`always @(posedge clk or reset)`	Missing `posedge` for reset
`always @(clk)`	Should use `posedge clk` for flip-flops

Challenge

What to do:

Add the correct sensitivity list to make this flip-flop work. The block should execute on the rising edge of clk.

Try it yourself

module flipflop (
  input clk,
  input d,
  output reg q
);
  
  always @(______) begin
    q <= d;
  end

endmodule

Test yourself

This lesson includes a short quiz. Start the lesson to answer it and track your progress.

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Your First Module Comments Design Abstraction Levels

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

3Number System

Binary Representation Sized Numbers Unsized Numbers Negative Numbers Special Values X And Z Recap - Number Formats

6Modules

Module Structure Input And Output Ports Inout Ports Module Instantiation Port Mapping By Name Port Mapping By Order Recap - Build A Module

9Procedural Blocks

Always Block Initial BlockSensitivity ListBlocking Assignment Non Blocking Assignment Recap - Always vs Initial

12Multiplexer Project

2 To 1 Mux Design 4 To 1 Mux Design

Using Case Statement

15Traffic Light Controller

Defining The States State Machine Logic

Timing The Transitions

Writing The Testbench

Verifying The Output

Practice on your own: Online Verilog compiler