Sensitivity List
Part of the Fundamentals section of Coddy's Verilog journey — lesson 48 of 90.
The sensitivity list tells the always block when to execute. It is written inside parentheses after the @ symbol.
The sensitivity list is a set of signals or events that trigger the always block. When any signal in the list changes, the block executes.
Syntax:
always @(sensitivity_list) begin
// Code runs when signals in the list change
endTypes of Sensitivity List
| Type | Syntax | When Block Executes |
|---|---|---|
| All signals (combinational) | always @(*) | When any signal inside changes |
| Specific signals | always @(a or b) | When a or b changes |
| Edge trigger (sequential) | always @(posedge clk) | On rising edge of clock |
| Multiple edges | always @(posedge clk or posedge reset) | On clock edge or reset edge |
Option 1: All Signals (*)
The safest and most common for combinational logic.
always @(*) begin
out = a & b; // Runs when a or b changes
endThe * automatically includes all signals read in the block.
Option 2: Specific Signals
always @(a or b) begin
out = a & b; // Runs when a or b changes
endIf you forget a signal, you get a latch (unintended memory).
Option 3: Edge Trigger (posedge)
always @(posedge clk) begin
q <= d; // Runs on rising edge of clock
endUse posedge for rising edge, negedge for falling edge.
Option 4: Multiple Edges
always @(posedge clk or posedge reset) begin
if (reset)
q <= 0;
else
q <= d;
endRuns on clock edge or reset edge.
Common Mistakes
| Mistake | Why Wrong |
|---|---|
always @(a or b or c) but uses d | Missing d → latch |
always @(posedge clk or reset) | Missing posedge for reset |
always @(clk) | Should use posedge clk for flip-flops |
Challenge
What to do:
- Add the correct sensitivity list to make this flip-flop work. The block should execute on the rising edge of
clk.
Cheat sheet
The sensitivity list follows @ and defines when an always block executes:
always @(sensitivity_list) begin
// executes when listed signals change
end| Type | Syntax | Triggers when |
|---|---|---|
| All signals | always @(*) | Any read signal changes |
| Specific signals | always @(a or b) | a or b changes |
| Rising edge | always @(posedge clk) | Rising edge of clk |
| Multiple edges | always @(posedge clk or posedge reset) | Either edge fires |
Use @(*) for combinational logic; use posedge/negedge for sequential logic:
// Combinational
always @(*) begin
out = a & b;
end
// Sequential (flip-flop with async reset)
always @(posedge clk or posedge reset) begin
if (reset) q <= 0;
else q <= d;
endCommon mistakes: missing a signal in a specific list causes a latch; writing always @(clk) instead of always @(posedge clk) for flip-flops; omitting posedge before reset in a multi-edge list.
Try it yourself
module flipflop (
input clk,
input d,
output reg q
);
always @(______) begin
q <= d;
end
endmodule
Test yourselfThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic
Timing The TransitionsWriting The TestbenchVerifying The Output