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Sensitivity List

Part of the Fundamentals section of Coddy's Verilog journey — lesson 48 of 90.

The sensitivity list tells the always block when to execute. It is written inside parentheses after the @ symbol.

The sensitivity list is a set of signals or events that trigger the always block. When any signal in the list changes, the block executes.

Syntax:

always @(sensitivity_list) begin
  // Code runs when signals in the list change
end

Types of Sensitivity List

TypeSyntaxWhen Block Executes
All signals (combinational)always @(*)When any signal inside changes
Specific signalsalways @(a or b)When a or b changes
Edge trigger (sequential)always @(posedge clk)On rising edge of clock
Multiple edgesalways @(posedge clk or posedge reset)On clock edge or reset edge

Option 1: All Signals (*)

The safest and most common for combinational logic.

always @(*) begin
  out = a & b;   // Runs when a or b changes
end

The * automatically includes all signals read in the block.

Option 2: Specific Signals

always @(a or b) begin
  out = a & b;   // Runs when a or b changes
end

If you forget a signal, the output does not update in simulation when that signal changes — so the simulation no longer matches the synthesized hardware.

Option 3: Edge Trigger (posedge)

always @(posedge clk) begin
  q <= d;        // Runs on rising edge of clock
end

Use posedge for rising edge, negedge for falling edge.

Option 4: Multiple Edges

always @(posedge clk or posedge reset) begin
  if (reset)
    q <= 0;
  else
    q <= d;
end

Runs on clock edge or reset edge.

Common Mistakes

MistakeWhy Wrong
always @(a or b or c) but uses dMissing d → output goes stale in simulation (sim/synth mismatch)
always @(posedge clk or reset)Missing posedge for reset
always @(clk)Should use posedge clk for flip-flops
challenge icon

Challenge

What to do:

  1. Add the correct sensitivity list to make this flip-flop work. The block should execute on the rising edge of clk.

Try it yourself

module flipflop (
  input clk,
  input d,
  output reg q
);
  
  always @(______) begin
    q <= d;
  end

endmodule
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This lesson includes a short quiz. Start the lesson to answer it and track your progress.

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