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Designing The Logic

Part of the Fundamentals section of Coddy's Verilog journey — lesson 44 of 90.

Challenge

Designing the logic means figuring out what equations the circuit needs based on the truth table.

Truth Table:

a	b	sum	carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Step 2: Find the pattern for sum

sum = 1 when a=0,b=1 or a=1,b=0
sum = 1 when a and b are different
Different = XOR → sum = a ^ b

Step 3: Find the pattern for carry

carry = 1 only when a=1 and b=1
Both = AND → carry = a & b

Step 4: Write equations

sum = a ^ b

carry = a & b

What to do:

Your task is to add the missing logic equations inside the module.

1. Add an assign statement for sum (a XOR b)
2. Add an assign statement for carry (a AND b)

Try it yourself

module half_adder (
  input a,
  input b,
  
  output sum,
  output carry
);

endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays Parameters Recap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The ModuleDesigning The Logic Project lesson

Project lesson

Writing The Testbench

Project lesson

11Loops

For Loop While Loop Repeat Loop Forever Loop Disable Statement Recap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counter State Machine

Project lesson

Transmitter Design

Project lesson

Project lesson