Bitwise Operators
Part of the Fundamentals section of Coddy's Verilog journey — lesson 23 of 90.
Bitwise operators perform operations on each individual bit of a number. Unlike arithmetic operators (+, -, *, /) that treat numbers as whole values, bitwise operators work bit-by-bit.
Available Bitwise Operators
| Operator | Operation | What It Does |
|---|---|---|
& | AND | Output bit is 1 only if both input bits are 1 |
| | OR | Output bit is 1 if at least one input bit is 1 |
^ | XOR | Output bit is 1 if input bits are different |
~ | NOT | Flips all bits (0 becomes 1, 1 becomes 0) |
When you use bitwise operators, Verilog treats the numbers as binary behind the scenes.
reg [3:0] a, b;
a = 4'd10; // Decimal 10 = binary 1010
b = 4'd12; // Decimal 12 = binary 1100
c = a & b; // Works the same as using binary directlyYou can write numbers in decimal, hex, or binary—Verilog converts them to binary for bitwise operations.
How Bitwise Works
Each operator works on pairs of bits (or single bits for NOT):
Example with 4-bit numbers:
a = 1010 (binary)
b = 1100 (binary)
AND: a & b = 1000
(1&1=1, 0&1=0, 1&0=0, 0&0=0)
OR: a | b = 1110
(1|1=1, 0|1=1, 1|0=1, 0|0=0)
XOR: a ^ b = 0110
(1^1=0, 0^1=1, 1^0=1, 0^0=0)
NOT: ~a = 0101
(~1=0, ~0=1, ~1=0, ~0=1)Code Example
module bitwise_demo;
reg [3:0] a, b;
reg [3:0] and_res, or_res, xor_res, not_res;
initial begin
a = 4'b1010;
b = 4'b1100;
and_res = a & b; // 1010 & 1100 = 1000
or_res = a | b; // 1010 | 1100 = 1110
xor_res = a ^ b; // 1010 ^ 1100 = 0110
not_res = ~a; // ~1010 = 0101
$display("a = %b", a);
$display("b = %b", b);
$display("a & b = %b", and_res);
$display("a | b = %b", or_res);
$display("a ^ b = %b", xor_res);
$display("~a = %b", not_res);
$finish;
end
endmoduleOutput:
a = 1010
b = 1100
a & b = 1000
a | b = 1110
a ^ b = 0110
~a = 0101Challenge
Calculate the bitwise results for the given values.
What to do:
- Calculate
a & band store inand_res - Calculate
a | band store inor_res - Calculate
a ^ band store inxor_res - Calculate
~aand store innot_res
Cheat sheet
Bitwise operators work on each individual bit of a number:
| Operator | Operation | Output bit is 1 when... |
|---|---|---|
& | AND | Both input bits are 1 |
| | OR | At least one input bit is 1 |
^ | XOR | Input bits are different |
~ | NOT | Flips all bits (unary) |
// a = 1010, b = 1100
a & b = 1000 // AND
a | b = 1110 // OR
a ^ b = 0110 // XOR
~a = 0101 // NOT
Try it yourself
module bitwise_challenge;
reg [3:0] a, b;
reg [3:0] and_res, or_res, xor_res, not_res;
initial begin
a = 4'b1101;
b = 4'b1011;
and_res = ______; // a & b
or_res = ______; // a | b
xor_res = ______; // a ^ b
not_res = ______; // ~a
$display("a = %b", a);
$display("b = %b", b);
$display("a & b = %b", and_res);
$display("a | b = %b", or_res);
$display("a ^ b = %b", xor_res);
$display("~a = %b", not_res);
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic