What Is Verilog

Part of the Fundamentals section of Coddy's Verilog journey — lesson 1 of 90.

Verilog is a hardware description language (HDL) used to model, design, and simulate digital electronic circuits — from simple logic gates to complex processors.

Unlike software languages that run sequentially on a CPU, Verilog describes hardware that operates in parallel. It is the industry standard for FPGA and ASIC design, used in tools like ModelSim, Vivado, and Quartus.

In this course, you will learn Verilog from the ground up — starting with basic simulation output, then building combinational and sequential circuits, and eventually designing real modules like counters, shift registers, and UART interfaces.

Challenge

Easy

Welcome to your first Verilog program! The code is already written for you.

What to do:

Look at the code — it uses $display to print text, similar to printf in C
Click Run Code to compile and simulate it
You should see Hello World! in the output

Note: Every Verilog program runs inside a module. The initial block runs once at the start of simulation, and $finish ends it.

Cheat sheet

Verilog is a hardware description language (HDL) that describes hardware operating in parallel, used for FPGA and ASIC design.

Every Verilog program runs inside a module. The initial block runs once at simulation start; $finish ends the simulation. Use $display to print text (similar to printf in C):

module example;
  initial begin
    $display("Hello World!");
    $finish;
  end
endmodule

Try it yourself

module main;
  initial begin
    $display("Hello World!");
    $finish;
  end
endmodule

All lessons in Fundamentals

1Introduction

What Is VerilogHardware vs Software Design Abstraction Levels Your First Module Comments

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register