Recap - Full Testbench

Part of the Fundamentals section of Coddy's Verilog journey — lesson 78 of 90.

Challenge

This challenge tests everything you have learned about testbenches: stimulus, display, monitor, dumpfile, dumpvars, and system tasks. You are given an XOR gate module to test.
What to do:

Create a complete testbench that:

Declares signals (reg for inputs, wire for output)
Instantiates the XOR gate with name dut
Creates a waveform file named xor_waveform.vcd
Dumps all signals in the testbench
Prints a header: "Testing XOR Gate"
Uses $monitor to track time, x, y, and z
Tests all four input combinations (00, 01, 10, 11) with #10 delay between each
Prints "Test complete" at the end
Ends the simulation with $finish

Try it yourself

module xor_gate (
  input x,
  input y,
  output z
);
  assign z = x ^ y;
endmodule

module testbench;
  // TODO: Declare reg for x and y
  
  // TODO: Declare wire for z
  

  // TODO: Instantiate xor_gate with name dut
  // Connect .x(x), .y(y), .z(z)


  initial begin
    // TODO: Add $dumpfile "xor_waveform.vcd"
    
    // TODO: Add $dumpvars (0, testbench)
    
    // TODO: Add $display "Testing XOR Gate"
    
    // TODO: Add $monitor for time, x, y, z
    // Format: "Time %0t: x=%b, y=%b, z=%b"
    
    // TODO: Add stimulus for all four combinations
    // 00, 01, 10, 11 with #10 delay
    
    // TODO: Add $display "Test complete"
    
    // TODO: Add $finish
    
  end
endmodule