Arrays
Part of the Fundamentals section of Coddy's Verilog journey. Lesson 10 of 90.
An array lets you store multiple values in one variable. Each element in the array can be accessed by its index.
Note: An array is not a separate data type. It is a collection of wire, reg, integer, or real types.
Declaring Arrays
Syntax: <data_type> <name> [<size>];
reg [7:0] memory [0:255]; // 256 bytes of memory (each 8 bits)
reg data [0:7]; // 8 single-bit registers
wire [3:0] bus [0:3]; // 4 buses, each 4 bits wide
integer counters [0:9]; // 10 integersThe number in brackets [ ] is the array size, not the bit width.
Accessing Array Elements
reg [7:0] memory [0:3];
memory[0] = 165; // Decimal 165
memory[1] = 90; // Decimal 90
memory[2] = memory[0] + memory[1];
$display("%d", memory[2]); // Prints: 255Arrays are very useful in testbenches for storing test data.
Multi-Dimensional Arrays
You can create arrays with multiple dimensions:
reg [7:0] matrix [0:3][0:3]; // 4x4 array of 8-bit values
matrix[0][0] = 255; // 8'hFF = 255 decimal
matrix[2][1] = 85; // 8'h55 = 85 decimalArray vs Vector
| Vector | Array | |
|---|---|---|
| What it is | Multi-bit wire or reg | Collection of multiple values |
| Syntax | [MSB:LSB] | [size] |
| Example | reg [7:0] data; | reg [7:0] mem [0:255]; |
| Access | data[3] (bit 3) | mem[3] (element 3) |
A vector is one value with multiple bits.
An array is multiple values, each with its own bits.
Important Notes
- Arrays are not synthesizable in many tools when used with large sizes
- Arrays are mostly used in testbenches
- For hardware memory, use special memory primitives
Challenge
Complete the code below to create an array that stores 4 test values.
What to do:
- Declare an array called
test_data- Use the
regdata type (because it stores values in a testbench) - Each element should be 8 bits wide (
[7:0]) - The array should have 4 elements (
[0:3])
- Use the
Try it yourself
module arrays;
// Declare an array called test_data
// It should have 4 elements, each 8 bits wide
// Use the reg data type (because it stores values in a testbench)
integer i;
initial begin
test_data[0] = 170;
test_data[1] = 240;
test_data[2] = 204;
test_data[3] = 15;
for (i = 0; i < 4; i = i + 1) begin
$display("test_data[%0d] = %b", i, test_data[i]);
end
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine LogicPractice on your own: Online Verilog compiler