Port Mapping By Order

Part of the Fundamentals section of Coddy's Verilog journey — lesson 35 of 90.

In the previous lesson, you learned about port mapping by name, where you explicitly label each connection using .port(signal). Now we will cover the alternative method: port mapping by order.

It connects signals to a module's ports based on the order they appear in the module definition. You simply list the signals in parentheses, and Verilog matches them one by one.

Syntax:

module_name instance_name (signal1, signal2, signal3);

The first signal connects to the first port, the second to the second port, and so on.

Example

Module definition:

module or_gate (
  input in1,      // First port
  input in2,      // Second port
  output result   // Third port
);
  assign result = in1 | in2;
endmodule

Instantiation with port mapping by order:

or_gate or1 (input_a, input_b, output_y);

This connects:

First signal input_a → first port in1
Second signal input_b → second port in2
Third signal output_y → third port result

Order Matters

With port mapping by order, the sequence is critical:

// Correct order
or_gate or1 (input_a, input_b, output_y);

// Wrong order - signals connected to wrong ports!
or_gate or1 (input_b, input_a, output_y);
or_gate or1 (output_y, input_a, input_b);

If you mix up the order, connections go to the wrong ports. This can be hard to debug because the code looks correct at first glance.

Port Mapping By Name vs By Order

Feature	By Name	By Order
Syntax	`.port(signal)`	`signal1, signal2`
Order matters?	No	Yes
Self-documenting?	Yes	No
Risk of mistakes	Low	High
Recommended for	Most designs	Simple cases only

When to Use Port Mapping By Order

Port mapping by order is acceptable when:

The module has very few ports (2-3)
The port order is obvious and unlikely to change
You are writing quick testbenches

For most designs, port mapping by name is preferred because it is clearer and less error-prone.

Challenge

Complete the instantiation by listing the signals in the correct order using port mapping by order.

What to do:

Module ports (in this order):

input en (enable)
input [7:0] d (data input)
output [7:0] q (data output)

Signals to connect:

enable_signal → connect to en
data_input → connect to d
data_output → connect to q

Cheat sheet

Port mapping by order connects signals based on their position matching the module's port definition order:

module_name instance_name (signal1, signal2, signal3);

Example with an or_gate module (ports: in1, in2, result):

or_gate or1 (input_a, input_b, output_y);

Order is critical — swapping signals causes wrong connections that are hard to debug.

Feature	By Name	By Order
Syntax	`.port(signal)`	`signal1, signal2`
Order matters?	No	Yes
Risk of mistakes	Low	High
Recommended for	Most designs	Simple/few ports only

Try it yourself

module register (
  input en,
  input [7:0] d,
  output [7:0] q
);
  assign q = en ? d : q;
endmodule

module top (
  input enable_signal,
  input [7:0] data_input,
  output [7:0] data_output
);
  
  // TODO: Instantiate register with name reg1 using ORDER mapping
  // List signals in correct order: enable_signal, data_input, data_output
  // Do not use .port(signal) syntax

endmodule