Arithmetic Operators
Part of the Fundamentals section of Coddy's Verilog journey — lesson 19 of 90.
Verilog provides basic arithmetic operators: + (addition), - (subtraction), * (multiplication) and / (division).
Code Example:
module arithmetic_demo;
reg [3:0] a, b;
reg [7:0] add, sub, mul, div;
initial begin
a = 4'd9;
b = 4'd4;
add = a + b; // 9 + 4 = 13
sub = a - b; // 9 - 4 = 5
mul = a * b; // 9 * 4 = 36
div = a / b; // 9 / 4 = 2
$display("9 + 4 = %d", add);
$display("9 - 4 = %d", sub);
$display("9 * 4 = %d", mul);
$display("9 / 4 = %d", div);
$finish;
end
endmoduleOutput:
9 + 4 = 13 9 - 4 = 5 9 * 4 = 36 9 / 4 = 2
Important Notes
- Division performs integer division (no fractions)
- Ensure the result register is wide enough for multiplication results
Challenge
In this challenge, you need to write the correct arithmetic expressions using the operators +, -, * and /.
What to do:
- Calculate
a + band store inadd - Calculate
a - band store insub - Calculate
a * band store inmul - Calculate
a / band store indiv
Cheat sheet
Verilog arithmetic operators: +, -, *, /
reg [3:0] a, b;
reg [7:0] add, sub, mul, div;
add = a + b;
sub = a - b;
mul = a * b;
div = a / b; // integer division (no fractions)Note: Ensure the result register is wide enough, especially for multiplication.
Try it yourself
module arithmetic_challenge;
reg [3:0] a, b;
reg [7:0] add, sub, mul, div;
initial begin
a = 4'd12;
b = 4'd5;
add = ______; // a + b
sub = ______; // a - b
mul = ______; // a * b
div = ______; // a / b
$display("12 + 5 = %d", add);
$display("12 - 5 = %d", sub);
$display("12 * 5 = %d", mul);
$display("12 / 5 = %d", div);
$finish;
end
endmoduleThis lesson includes a short quiz. Start the lesson to answer it and track your progress.
All lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic