Recap - Loop Patterns
Part of the Fundamentals section of Coddy's Verilog journey — lesson 63 of 90.
Challenge
Complete the missing parts in each loop to produce the expected output.
What to do:
- Use a
forloop to print numbers 0 to 3 - Use a
whileloop to print numbers 0 to 2 - Use a
repeatloop to print "Hello" 3 times
Try it yourself
module loop_patterns;
integer i;
initial begin
$display("For Loop:");
// TODO: Add for loop (i=0 to 3)
$display("While Loop:");
i = 0;
// TODO: Add while loop (i=0 to 2)
$display("Repeat Loop:");
// TODO: Add repeat loop (print "Hello" 3 times)
$finish;
end
endmoduleAll lessons in Fundamentals
4Operators Part 1
Arithmetic OperatorsModulo OperatorComparison OperatorsRecap - Simple MathBitwise Operators7Assign And Gates
Continuous AssignmentAssign With OperatorsBuilt In Gate PrimitivesAND OR NOT GatesXOR XNOR GatesRecap - Logic Gate Circuit10Decision Making
If StatementIf - ElseRecap - Simple ComparatorCase StatementCasex And CasezRecap - ALU Design5Operators Part 2
Logical OperatorsReduction OperatorsShift OperatorsConcatenation OperatorConditional OperatorRecap - Operator Challenge3Number System
Binary RepresentationSized NumbersUnsized NumbersNegative NumbersSpecial Values X And ZRecap - Number Formats6Modules
Module StructureInput And Output PortsInout PortsModule InstantiationPort Mapping By NamePort Mapping By OrderRecap - Build A Module9Procedural Blocks
Always BlockInitial BlockSensitivity ListBlocking AssignmentNon Blocking AssignmentRecap - Always vs Initial15Traffic Light Controller
Defining The StatesState Machine Logic