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Recap - Loop Patterns

Part of the Fundamentals section of Coddy's Verilog journey. Lesson 63 of 90.

Challenge

Complete the missing parts in each loop to produce the expected output.

What to do:

Use a for loop to print numbers 0 to 3
Use a while loop to print numbers 0 to 2
Use a repeat loop to print "Hello" 3 times

Try it yourself

module loop_patterns;
  integer i;
  
  initial begin
    $display("For Loop:");
    // TODO: Add for loop (i=0 to 3)
    
    
    $display("While Loop:");
    i = 0;
    // TODO: Add while loop (i=0 to 2)
    
    
    $display("Repeat Loop:");
    // TODO: Add repeat loop (print "Hello" 3 times)
    
    
    $finish;
  end
endmodule

All lessons in Fundamentals

1Introduction

What Is Verilog Hardware vs Software Your First Module Comments Design Abstraction Levels

4Operators Part 1

Arithmetic Operators Modulo Operator Comparison Operators Recap - Simple Math Bitwise Operators

7Assign And Gates

Continuous Assignment Assign With Operators Built In Gate Primitives AND OR NOT Gates XOR XNOR Gates Recap - Logic Gate Circuit

10Decision Making

If Statement If - Else Recap - Simple Comparator Case Statement Casex And Casez Recap - ALU Design

13Timing And Delays

What Are Delays Gate Delays Assignment Delays Timescale Directive Clock Generation Recap - Timing Control

16Final Challenges

4 Bit Counter Decoder Design Shift Register

2Data Types

Wire Type Reg Type Integer And Real Vectors Arrays Parameters Recap - Declare Signals

5Operators Part 2

Logical Operators Reduction Operators Shift Operators Concatenation Operator Conditional Operator Recap - Operator Challenge

8Half Adder Project

Writing The Module Designing The Logic

Project lesson

Writing The Testbench

Project lesson

11Loops

For Loop While Loop Repeat Loop Forever Loop Disable StatementRecap - Loop Patterns

14Testbench Basics

What Is A Testbench Creating Stimulus Display And Monitor Dumpfile And Dumpvars Using System Tasks Recap - Full Testbench

17UART

Bit counter State Machine

Project lesson

Transmitter Design

Project lesson

Project lesson

Practice on your own: Online Verilog compiler